US3691297A
Expired / Lapsed
US
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Synchronization phase-lock system for a digital vertical synchronization system
Assignee: Zenith Electronics LLC
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Filing: 1971-05-06
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Granted: 1972-09-12
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Expires: 1991-05-06
Abstract
Abstract A synchronization phase-lock system in a television receiver for maintaining coincidence between locally-generated vertical synchronization pulses and vertical synchronization pulses developed from received television transmissions. The phase-lock system utilizes the received vertical sync pulses in conjunction with gating circuitry to condition an up/down binary counter to count, within predetermined limits, in a first, or ''''up'''', direction during the received vertical sync interval and in the opposite, or ''''down'''' direction during the vertical trace interval of the received signal. Locally generated vertical sync pulses are also applied to the up/down binary counter wherein each pulse initiates one count. A locally generated vertical sync pulse occurring during the received vertical sync pulse interval generates one ''''up'''' count representative of coincidence between the received and locally generated vertical sync pulses. If the locally generated vertical sync pulse occurs during the vertical trace interval, a ''''down'''' count indicating non-coincidence is initiated. The phase-lock system further includes a reset gating circuit activated by the up/down binary counter reaching its ''''down'''' counting limit for resetting the phase of the locally generated vertical sync pulses such that they will be coincident with the received vertical sync pulses.
Inventors
- 👤 Richard G Merrell
- 👤 Melvin C Hendrickson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:50
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/12
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
226 words
In a digital vertical synchronization system having a source of locally generated vertical sync pulses coupled to a vertical sweep system and a further source of derived vertical sync pulses developed from a received television signal, a synchronization phase-lock system, comprising in combination: circuit means coupled to said source of derived vertical sync pulses for developing a control signal having a first signal level during the sync intervals of said derived vertical sync pulses and a second signal level during the trace intervals; counter means coupled to said circuit means and to said source of locally generated vertical sync pulses, said first signal level of said applied control signal conditioning said counter means to count ''''up'''' to a maximum confidence level when the locally generated vertical sync pulses are in time coincidence with the derived sync pulses and said second signal level of said applied control signal conditioning said counter means to count ''''down'''' to a minimum confidence level upon noncoincidence, each of said locally generated vertical sync pulses initiating one count by said counter means; and gating means coupled between said counter means and said source of locally generated vertical sync pulses for correcting the phase of said locally generated vertical sync pulses so as to be coincident with said derived vertical sync pulses whenever said counter means reaches a condition of minimum confidence level.
Claim 2
Dependent Claim
226 words
In a digital vertical synchronization system having a source of locally generated vertical sync pulses coupled to a vertical sweep system and a further source of derived vertical sync pulses developed from a received television signal, a synchronization phase-lock system, comprising in combination: circuit means coupled to said source of derived vertical sync pulses for developing a control signal having a first signal level during the sync intervals of said derived vertical sync pulses and a second signal level during the trace intervals; counter means coupled to said circuit means and to said source of locally generated vertical sync pulses, said first signal level of said applied control signal conditioning said counter means to count ''''up'''' to a maximum confidence level when the locally generated vertical sync pulses are in time coincidence with the derived sync pulses and said second signal level of said applied control signal conditioning said counter means to count ''''down'''' to a minimum confidence level upon noncoincidence, each of said locally generated vertical sync pulses initiating one count by said counter means; and gating means coupled between said counter means and said source of locally generated vertical sync pulses for correcting the phase of said locally generated vertical sync pulses so as to be coincident with said derived vertical sync pulses whenever said counter means reaches a condition of minimum confidence level.
Claim 3
Dependent Claim
65 words
A synchronization phase-lock system in accordance with claim 1 wherein maximum confidence gating means is coupled from said counter means to said circuit means, said maximum confidence gating means developing an override signal upon said counter means reaching its maximum counting level to force said circuit means to condition said counter means to count ''''down'''' upon receipt of the next locally generated vertical sync pulse.
Claim 4
Dependent Claim
73 words
A synchronization phase-lock system in accordance with claim 1 wherein said circuit means includes a monostable multivibrator and an up/down gate serially connected between the source of derived vertical sync pulses and said counter means, said monostable multivibrator developing output pulses during the sync intervals of the derived vertical sync pulses and applying said output pulses to said up/down gate for conditioning said counter means to count ''''up'''' only during said sync intervals.
Claim 5
Dependent Claim
87 words
A synchronization phase-lock system in accordance with claim 3 wherein said up/down gate includes a NOR gate and an inverter interconnected between said monostable multivibrator and said counter means, said NOR gate being activated by negative output pulses from said monostable multivibrator to apply a high level ''''up'''' control signal directly to one input of said counter means and through said inverter to a second input of said counter means, said control signal being effective to condition said counter means to count ''''up'''' during said sync intervals.
Claim 6
Dependent Claim
111 words
A synchronization phase-lock system in accordance with claim 4 wherein said maximum confidence gating means includes a NAND gate and an inverter serially connected between the outputs of said counting means and the input of said up/down gate, said maximum confidence gating means reacting to high level outputs of said counter means corresponding to its maximum counting level for generating a high level override signal at the input of said NOR gate, said high level override signal forcing said up/down gate to condition said counter means to count ''''down'''' upon receipt of the next locally generated vertical sync pulse regardless of its phase relationship with the corresponding derived vertical sync pulse.
Claim 7
Dependent Claim
124 words
A synchronization phase-lock system in accordance with cLaim 3 wherein said gating means includes a minimum confidence gate having respective inputs coupled to the outputs of said counter means and the output of said monostable multivibrator and further includes a reset gate interconnected between the output of said minimum confidence gate and the source of locally generated vertical sync pulses, said counter means upon reaching its minimum counting level being effective to condition said minimum confidence gate to generate a reset signal coincident with the next output pulse from said monostable multivibrator, said reset signal upon application to said reset gate generating a pulse for resetting the phase of the locally generated vertical sync pulses to be coincident with the derived vertical sync pulses.
Claim 8
Dependent Claim
46 words
A synchronization phase-lock system in accordance with claim 6 wherein said minimum confidence gate includes a NAND gate connected to an RS flip-flop, said RS flip-flop stretching said reset signal to a predetermined length for assuring that all logic is appropriately reset by said reset signal.
Claim 9
Dependent Claim
45 words
A synchronization phase-lock system in accordance with claim 7 wherein means connecting the output of said RS flip-flop to the reset terminal of said counter means is included for resetting said counter means to an arbitrary counting level whenever the minimum counting level is reached.
Claim 10
Dependent Claim
17 words
A synchronization phase-lock system in accordance with claim 6 wherein said reset gate includes a NOR gate.
Claim 11
Dependent Claim
26 words
A synchronization phase-lock system in accordance with claim 1 wherein the digital vertical synchronization system including said synchronization phase-lock system is fabricated in integrated circuit form.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-09-12 | 1976-03-13 | 1976-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-09-12 | 1980-03-13 | 1980-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-09-12 | 1984-03-13 | 1984-09-12 | $7700.00 | Window Closed / Lapsed |