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US3886532A
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Integrated four-phase digital memory circuit with decoders
Assignee: Unisys Corp
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Filing: 1974-05-08
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Granted: 1975-05-27
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Expires: 1994-05-08
Abstract
Abstract A memory circuit includes an array of variable threshold field effect memory transistors of a known type, arranged in word rows and bit columns. The gate electrodes of all memory transistors in a given word-row are connected to a word-line common to that row. The source and drain electrodes of all memory transistors in a given bit-column are connected to source and drain lines, respectively, common to that column. Each word-line is coupled through an individual buffer transistor to a decoding matrix by means of which a selected word-line may be charged to a desired voltage level. The source and drain lines are connected to bit decoding networks by means of which the source and drain lines may be connected to predetermined voltages suitable for use in writing or interrogation. Writing voltages are applied to the circuit in a four-phase operating sequence. During the first phase, both the memory substrate and the transistor gates are charged to the same specified voltage level. In the second phase, the memory transistors in the selected word-line are set to their low threshold value so as to clear this word-line. During the third phase, the gates and substrates of the memory transistors are reduced to zero voltage; however, the sources and drains of the memory transistors are maintained at a relatively high voltage. During the fourth phase, the gates of the memory transistors in the selected row are driven negative while the remaining gates are maintained at zero voltage. If a binary ZERO is to be written into the addressed bit, the sources of all memory transistors in the corresponding row are grounded while the sources in the remaining bit columns are left in their charged state. If a binary ONE is to be written into the addressed bit, the sources and drains of all of the memory transistors are left in their charged state. Reading may be accomplished by applying voltages of a lower magnitude in the same four-phase sequence and adjusting the control voltages.
Inventors
- 👤 Horst A R Wegener
- 👤 Douglas R Askegard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:29
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
307 words
A digital memory circuit of the type employing variable threshold insulated gate field effect memory transistors arranged in word rows and bit columns on a common substrate, each of said memory transistors including gate, source and drain electrodes, said circuit comprising: a clocked voltage source for supplying READ and WRITE sequential pulse trains to components in said memory circuit, word line decoder means, individual buffer transistor means for applying gate control voltages from said clocked voltage source to corresponding word rows of memory transistors in response to output signals from said word line decoder means, bit line decoder means for selectively intercoupling individual bit columns of said memory array with external utilization circuits, said clocked voltage source including means to apply decoder control voltages and substrate control voltages to said word line decoder and said common substrate, said word line decoder means including means for turning on all of said buffer transistors in response to a decoder control voltage from said clock voltage source, said decoder means further including means response to a received address signal for temporarily retaining a specified buffer transistor in a conducting condition after the termination of a decoder control voltage, said specified transistor being uniquely determined by the value of said address signal, whereby only the addressed word line receives a gate control voltage during such temporary retention times, said clock voltage source being arranged to provide gate control voltages and substrate control voltages of opposite polarity during such temporary retention times, said clocked voltage source further being arranged to produce gate control and substrate control voltages during a WRITE sequence in which the differential pulse magnitudes are sufficient to shift the conduction threshold of the memory transistors whereby the binary state of the transistors in the word row corresponding to said address signal may be reversed during such temporary retention times.
Claim 2
Dependent Claim
307 words
A digital memory circuit of the type employing variable threshold insulated gate field effect memory transistors arranged in word rows and bit columns on a common substrate, each of said memory transistors including gate, source and drain electrodes, said circuit comprising: a clocked voltage source for supplying READ and WRITE sequential pulse trains to components in said memory circuit, word line decoder means, individual buffer transistor means for applying gate control voltages from said clocked voltage source to corresponding word rows of memory transistors in response to output signals from said word line decoder means, bit line decoder means for selectively intercoupling individual bit columns of said memory array with external utilization circuits, said clocked voltage source including means to apply decoder control voltages and substrate control voltages to said word line decoder and said common substrate, said word line decoder means including means for turning on all of said buffer transistors in response to a decoder control voltage from said clock voltage source, said decoder means further including means response to a received address signal for temporarily retaining a specified buffer transistor in a conducting condition after the termination of a decoder control voltage, said specified transistor being uniquely determined by the value of said address signal, whereby only the addressed word line receives a gate control voltage during such temporary retention times, said clock voltage source being arranged to provide gate control voltages and substrate control voltages of opposite polarity during such temporary retention times, said clocked voltage source further being arranged to produce gate control and substrate control voltages during a WRITE sequence in which the differential pulse magnitudes are sufficient to shift the conduction threshold of the memory transistors whereby the binary state of the transistors in the word row corresponding to said address signal may be reversed during such temporary retention times.
Claim 3
Dependent Claim
118 words
The memory circuit of claim 1 wherein The clocked voltage source is constructed to provide a four-phase WRITE sequence in which decoder control voltages are produced only during the first and third of such phases so that said temporary retention times occur during the second and fourth of such phases, said clocked voltage source being further constructed so that the polarities of the gate control and substrate control voltages produced during the fourth phase are the reverse of the polarities produced during the second phase whereby the conduction thresholds of the memory transistors in the addressed word row may be shifted to one value during phase 2 and may be shifted to the opposite value during phase 4.
Claim 4
Dependent Claim
157 words
The memory circuit of claim 2 further containing means to couple decoder control voltages to the common source and drain lines of each bit column during the first and third phases of said WRITE sequence whereby the source and drain elements of all memory transistors become charged to a predetermined voltage during these phases, said memory circuit having sufficient capacitance so that the charge thus acquired by the common source and drain lines may be retained during the succeeding second and fourth phases respectively, said memory circuit further being characterized in that the clocked voltage source produces decoder control voltages and substrate control voltages of the same polarity during said first phase of the WRITE sequence so that the common source and drain lines and the substrate are charged to voltages of the same polarity during the first phase of the WRITE sequence and to voltages of the opposite polarity during the third phase of that sequence.
Claim 5
Dependent Claim
120 words
The memory system of claim 3 wherein said bit line decoding means includes individual in-out terminals corresponding to each bit column in the memory array for receiving WRITE signals during the fourth phase of said WRITE sequence, said bit line decoding means further including individual switching means corresponding to each in-out terminal for discharging the common source line in the corresponding bit column in response to a received WRITE signal having a first binary value opposite to that stored in the addressed memory transistor during the second phase of the WRITE sequence, said switching means further being arranged to permit retention of the charge on the associated common source line upon receipt of a WRITE pulse of opposite binary value.
Claim 6
Dependent Claim
59 words
The memory circuit of claim 4 wherein each switching means in said bit line decoder means includes first switching transistor means used only during a WRITE sequence and second switching transistor means used only during a READ sequence, and wherein said clocked voltage source further includes means for providing mode command signals for selectively actuating said switching transistor means.
Claim 7
Dependent Claim
52 words
The memory circuit of claim 5 wherein the READ sequence consists of a four-phase sequence in which the gate control and substrate control voltages are applied in the same sequence as the corresponding WRITE sequence but at a reduced magnitude insufficient to cause shifting of the conduction threshold of the memory transistors.
Claim 8
Dependent Claim
143 words
The memory circuit of claim 6 wherein the clocked voltage source includes means for providing a first negative mode command signal throughout the READ sequence and means for providing a second mode command signal consisting of a negative pulse during the third phase of the READ sequence, each of said second switching transistor means in the bit line decoder means including a transistor arranged to clamp the source line of the associated bit column to the level of the negative mode command signal during the entire READ sequence, each of said second switching means further including means for precharging transistors in that switching transistor means in response to the pulsed second mode command signal, and means for conditionally dissipating such precharge during the fourth phase of the READ cycle as determined by the value of the information stored in the addressed memory transistor.
Claim 9
Dependent Claim
76 words
The memory circuit of claim 9 wherein the READ sequence is a two-phase sequence in which the decoder control voltage consists of a negative pulse occurring only throughout the first phase, the gate control voltage consists of a negative pulse occurring during the second pulse and the substrate control voltage is maintained at zero level throughout the READ sequence, said gate control voltage having a magnitude insufficient to shift the conduction threshold of the memory transistors.
Claim 10
Dependent Claim
82 words
The memory circuit of claim 5 wherein the READ sequence is a four-phase sequence in which the decoder control voltage consists of negative pulses occurring during the first and third phases, the gate control voltage consists of negative pulses occurring during the first and fourth phases, and the substrate control voltage consists of a negative pulse occurring throughout the first and second phases, said gate control and substrate control voltages having magnitudes insufficient to shift the conduction threshold of the memory transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-26 | 1978-11-25 | 1979-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-26 | 1982-11-25 | 1983-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-26 | 1986-11-25 | 1987-05-27 | $7700.00 | Window Closed / Lapsed |