Bipolar transistor construction method

Claim 1

A METHOD OF FABRICATING A BIPOLAR TRANSISTOR IN INTERGRATED CIRUIT FORM BY A TRIPLE DEPOSITION PROCESS, COMPRISING: A. FORMING ON A SEMICONDUCTOR SUBSTRATE SURFACE OF FIRST CONDUCTIVITY TYPE A PERMANENT MASK FROM A LAYR OF A FIRST MASKING MATERIAL HAVING AN INNER BOUNDARY DEFINING A RECTANGULAR OPENING OF PRDETERMINED LENGTH AND WIDTH AND AN OUTER BOUNDARY SPACED EQUIDISTANT FORM SAID INNER BOUNDARY, SAID INNER AND OUTER BOUNDARIES DEFINING AN ANNULAR TOLERANCE REGION WITHIN WHICH MUST LIE EDGES OF SUBSEQUENT MASKS OF A SECOND MATERIAL, SAID FIRST MASKING MATERIAL BEING READILY ETCHABLE BY A FIRST ETCHANT, BY A SECOND ETCHANT, B. SUPERIMPOSING OVER SAID PERMANENT MASK A FIRST MASK OF A SECOND MASKING MATERIAL WITH ALL FOUR EDGES THEREOF LYING WITHIN SAID TOLERANCE REGION SO AS TO NASK REGIONS IN SAID SUBSTRAE SURROUNDING SAID PERMANENT MASK WHILE LEAVING UNMASKED THE ENTIRE AREA OF SAID SUBSTRATE LYING WITHIN SAID RECTANGULAR OPENING, SAID SECOND MASKING MATERIAL BEING READILY ETCHABLE BY SAID SECOND ETCHANT BUT NOT BY SAID FIRST ETCHANT, C. INTRODUCING FIRSTLY AN IMPURITY OF SECOND CONDUCTIVITY TYPE THROUGH SAID RECTANGULAR OPENING TO FORM A COLLECTOR REGION OF SECOND CONDUCTIVITY TYPE WITHIN SAID SUBSTRATE, D. SUPERIMPOSING OVER SAID PERMANENT MASK A SECOND MASK OF SAID SECOND MASKING MATERIAL WITH AT LEAST ONE EDGE THEREOF CROSSING SAID RECTANGULAR OPENING AND WITH THE REMAINING EDGES THEREOF LYING WITHIN SAID TOLERANCE REGION SO AS TO PARTIALLY MASK SAID RECTANGULAR OPENING WHILE LEAVING UNMASKED ONLY AN AREA PORTION OF SAID COLLECTOR REGION. E. INTRODUCING SECONDLY AN IMPURITY OF SAID FIRST CONDUCTIVITY TYPE INTO THE UNMASKED AREA PORTION OF SAID COLLECTOR REGION TO FORM A BASE REGION OF SAID FIRST CONDUCTIVITY TYPE WITHIN SAID COLLECTOR REGION. F. SUPERIMPOSING OVER SAID PERMANENT MASK A THIRD MASK OF SAID SECOND MASKING MATERIAL WITH AT LEAST THREE EDGES THEREOF CROSSING SAID RECTANGULAR OPENING AND WITH THE REMAINING EDGES THEREOF LYING WITHIN SAID TOLERANCE REGION SO AS TO PARTIALLY MASK SAID RECTANGULAR OPENING WHILE LEAVING UNMASKED AN AREA PORTION ONLY OF SAID COLLECTOR REGION AND AN AREA PORTION ONLY OF SAID BASE REGION, AND G. INTRODUCING THIRDLY AN IMPIRITY OF SAID SECOND CONDUCTIVITY TYPE INTO THE UNMASKED AREA PORTIONS OF SAID COLLECTOR AND BASE REGIONS TO FORM A COLLECTOR CONTACT REGION WITHIN SAID COLLECTOR REGION AND AN EMITTER REGION WITHIN SAID BASE REGION, RESPECTIVELY.

Claim 2

A METHOD OF FABRICATING A BIPOLAR TRANSISTOR IN INTERGRATED CIRUIT FORM BY A TRIPLE DEPOSITION PROCESS, COMPRISING: A. FORMING ON A SEMICONDUCTOR SUBSTRATE SURFACE OF FIRST CONDUCTIVITY TYPE A PERMANENT MASK FROM A LAYR OF A FIRST MASKING MATERIAL HAVING AN INNER BOUNDARY DEFINING A RECTANGULAR OPENING OF PRDETERMINED LENGTH AND WIDTH AND AN OUTER BOUNDARY SPACED EQUIDISTANT FORM SAID INNER BOUNDARY, SAID INNER AND OUTER BOUNDARIES DEFINING AN ANNULAR TOLERANCE REGION WITHIN WHICH MUST LIE EDGES OF SUBSEQUENT MASKS OF A SECOND MATERIAL, SAID FIRST MASKING MATERIAL BEING READILY ETCHABLE BY A FIRST ETCHANT, BY A SECOND ETCHANT, B. SUPERIMPOSING OVER SAID PERMANENT MASK A FIRST MASK OF A SECOND MASKING MATERIAL WITH ALL FOUR EDGES THEREOF LYING WITHIN SAID TOLERANCE REGION SO AS TO NASK REGIONS IN SAID SUBSTRAE SURROUNDING SAID PERMANENT MASK WHILE LEAVING UNMASKED THE ENTIRE AREA OF SAID SUBSTRATE LYING WITHIN SAID RECTANGULAR OPENING, SAID SECOND MASKING MATERIAL BEING READILY ETCHABLE BY SAID SECOND ETCHANT BUT NOT BY SAID FIRST ETCHANT, C. INTRODUCING FIRSTLY AN IMPURITY OF SECOND CONDUCTIVITY TYPE THROUGH SAID RECTANGULAR OPENING TO FORM A COLLECTOR REGION OF SECOND CONDUCTIVITY TYPE WITHIN SAID SUBSTRATE, D. SUPERIMPOSING OVER SAID PERMANENT MASK A SECOND MASK OF SAID SECOND MASKING MATERIAL WITH AT LEAST ONE EDGE THEREOF CROSSING SAID RECTANGULAR OPENING AND WITH THE REMAINING EDGES THEREOF LYING WITHIN SAID TOLERANCE REGION SO AS TO PARTIALLY MASK SAID RECTANGULAR OPENING WHILE LEAVING UNMASKED ONLY AN AREA PORTION OF SAID COLLECTOR REGION. E. INTRODUCING SECONDLY AN IMPURITY OF SAID FIRST CONDUCTIVITY TYPE INTO THE UNMASKED AREA PORTION OF SAID COLLECTOR REGION TO FORM A BASE REGION OF SAID FIRST CONDUCTIVITY TYPE WITHIN SAID COLLECTOR REGION. F. SUPERIMPOSING OVER SAID PERMANENT MASK A THIRD MASK OF SAID SECOND MASKING MATERIAL WITH AT LEAST THREE EDGES THEREOF CROSSING SAID RECTANGULAR OPENING AND WITH THE REMAINING EDGES THEREOF LYING WITHIN SAID TOLERANCE REGION SO AS TO PARTIALLY MASK SAID RECTANGULAR OPENING WHILE LEAVING UNMASKED AN AREA PORTION ONLY OF SAID COLLECTOR REGION AND AN AREA PORTION ONLY OF SAID BASE REGION, AND G. INTRODUCING THIRDLY AN IMPIRITY OF SAID SECOND CONDUCTIVITY TYPE INTO THE UNMASKED AREA PORTIONS OF SAID COLLECTOR AND BASE REGIONS TO FORM A COLLECTOR CONTACT REGION WITHIN SAID COLLECTOR REGION AND AN EMITTER REGION WITHIN SAID BASE REGION, RESPECTIVELY.

Claim 6

A method of fabricating a bipolar transistor in integrated circuit form by a triple deposition process, comprising: A. forming on a semiconductor substrate of first conductivity type a permanent mask from a layer of silicon nitride having an inner boundary defining a rectangular opening of width S and length 9S, and an outer boundary, spaced a distance S from said inner boundary, where S is about 0.1 mil, said inner and outer boundaries defining an annular tolerance region within which must lie edges of subsequent masks of silicon dioxide, said rectangular opening being capable of division into nine square zones of equal area arranged in a row and identified as zones 1 through 9 taken consecutively; B. superimposing over said permanent mask a first mask of silicon dioxide with all four edges thereof lying within said tolerance region so as to mask regions of said substrate surrounding said permanent mask while leaving unmasked the entire surface of said substrate lying within said rectangular opening; C. performing a first impurity deposition of second conductivity type through all nine zones of said rectangular opening to form a collector region of second conductivity type within said substrate; D. superimposing over said permanent mask a second mask of silicon dioxide with one edge thereof crossing said rectangular opening and with the remaining edges lying within said tolerance region so as to mask areas of said substrate surface coinciding with zones 1 and 2; E. performing a second impurity deposition of first conductivity type through zones 3 through 9 of said rectangular opening to form a base region within said collector region; F. superimposing over said permanent mask a third mask of silicon dioxide with three edges thereof crossing said rectangular opening and with the remaining edges lying within said tolerance region so as to mask areas of said substrate surface coinciding with zones 2, 3, 7, 8, 9 of said rectangular opening; G. performing a third impurity deposition of second conductivity type through zones 1, 4, 5, 6 of said rectangular opening to form a collector contact region within said collector region and an emitter region within said base region; H. superimposing over said permanent mask a fourth mask of silicon dioxide with four edges thereof crossing said rectangular opening and with the remaining edges thereof lying within said tolerance region so as to mask areas of said substrate surface coinciding with zones 2, 3, 4, 6, 7, 8 of said rectangular opening; and I. depositing metal through zones 1, 5, 9 of said rectangular opening to form metallic contacts to said collector contact, emitter, and base regions, respectively.

Claim 7

A method of fabricating a bipolar transistor in integrated circuit form by a triple deposition process, comprising: A. forming on a semiconductor substrate of first conductivity type a permanent mask from a layer of silicon nitride having an inner boundary defining a rectangular opening of width S and length 9S, and an outer boundary, spaced a distance S from said inner boundary, where S is about 0.1 mil, said inner and outer boundaries defining an annular tolerance region within which must lie edges of subsequent masks of silicon dioxide, said rectangular opening being capable of division into nine square zones of equal area arranged in a row and identified as zones 1 through 9 taken consecutively; B. superimposing over said permanent mask a first mask of silicon dioxide with all four edges thereof lying within said tolerance region so as to mask regions of said substrate surrounding said permanent mask while leaving unmasked the entire surface of said substrate lying within said rectangular opening; C. performing a first impurity deposition of second conductivity type through all nine zones of said rectangular opening to form a collector region of second conductivity type within said substrate; D. superimposing over said permanent mask a second mask of silicon dioxide with one edge thereof crossing said rectangular opening and with the remaining edges lying within said tolerance region so as to mask areas of said substrate surface coinciding with zones 1 and 2; E. performing a second impurity deposition of first conductivity type through zones 3 through 9 of said rectangular opening to form a base region within said collector region; F. superimposing over said permanent mask a third mask of silicon dioxide with three edges thereof crossing said rectangular opening and with the remaining edges lying within said tolerance region so as to mask areas of said substrate surface coinciding with zones 2, 3, 7, 8, 9 of said rectangular opening; G. performing a third impurity deposition of second conductivity type through zones 1, 4, 5, 6 of said rectangular opening to form a collector contact region within said collector region and an emitter region within said base region; H. superimposing over said permanent mask a fourth mask of silicon dioxide with four edges thereof crossing said rectangular opening and with the remaining edges thereof lying within said tolerance region so as to mask areas of said substrate surface coinciding with zones 2, 3, 4, 6, 7, 8 of said rectangular opening; and I. depositing metal through zones 1, 5, 9 of said rectangular opening to form metallic contacts to said collector contact, emitter, and base regions, respectively.

Claim 11

A method of fabricating a bipolar transistor in integrated circuit form by a triple deposition process, comprising: A. forming on a semiconductor substrate surface of first conductivity type a permanent mask from a layer of a first masking material in the form of a rectangular figure eight with one rectangular opening thereof being wider than the other one, said mask having an outer boundary spaced equidistant from each opening by a distance equal to the spacing between said openings to define a tolerance region within which must lie the edges of subsequent masks, said first material being readily etchable by a first etchant but not a second etchant; B. superimposing over said permanent mask a first mask of a second masking material with all edges thereof lying within said tolerance region so as to mask regions of said substrate surrounding said permanent mask while leaving unmasked the entire area of said substrate lying within said figure eight, said second masking material being readily etchable by said second etchant but not by said first etchant; C. performing a first impurity deposition of second conductivity type through both said rectangular openings to form a collector region within said substrate; D. superimposing over said permanent mask a second mask of said second masking material with all edges thereof lying within said tolerance region surrounding the wider one of said rectangular openings so as to mask the narrower one of said rectangular openings; E. performing a second impurity deposition of first conductivity type through said wider rectangular opening to form a base region within said collector region; F. superimposing a third mask of said second masking material over said permanent mask with one edge thereof crossing said wider rectangular opening and the remaining edges lying within said tolerance region so as to mask approximately a half area portion of said wider rectangular opening as measured along its length; and G. performing a third impurity deposition of second conductivity type through the unmasked half of said wider rectangular opening to form an emitter region within said base region and through said narrower opening to form a collector contact region within said collector region.

Claim 12

A method of fabricating a bipolar transistor in integrated circuit form by a triple deposition process, comprising: A. forming on a semiconductor substrate surface of first conductivity type a permanent mask from a layer of a first masking material in the form of a rectangular figure eight with one rectangular opening thereof being wider than the other one, said mask having an outer boundary spaced equidistant from each opening by a distance equal to the spacing between said openings to define a tolerance region within which must lie the edges of subsequent masks, said first material being readily etchable by a first etchant but not a second etchant; B. superimposing over said permanent mask a first mask of a second masking material with all edges thereof lying within said tolerance region so as to mask regions of said substrate surrounding said permanent mask while leaving unmasked the entire area of said substrate lying within said figure eight, said second masking material being readily etchable by said second etchant but not by said first etchant; C. performing a first impurity deposition of second conductivity type through both said rectangular openings to form a collector region within said substrate; D. superimposing over said permanent mask a second mask of said second masking material with all edges thereof lying within said tolerance region surrounding the wider one of said rectangular openings so as to mask the narrower one of said rectangular openings; E. performing a second impurity deposition of first conductivity type through said wider rectangular opening to form a base region within said collector region; F. superimposing a third mask of said second masking material over said permanent mask with one edge thereof crossing said wider rectangular opening and the remaining edges lying within said tolerance region so as to mask approximately a half area portion of said wider rectangular opening as measured along its length; and G. performing a third impurity deposition of second conductivity type through the unmasked half of said wider rectangular opening to form an emitter region within said base region and through said narrower opening to form a collector contact region within said collector region.