Complementary metal insulator silicon transistor pairs

Claim 1

A pair of complementary metal-insulator- silicon field effect transistors of the enhancement mode type with self-registered gates comprising: a. a semiconducting silicon substrate of N-type conductivity; b. an insulating layer comprising a thermally grown silicon oxide overlying said semiconducting substrate; c. an ionically implanted uniformly lightly doped pocket of Ptype conductivity positioned within said substrate and having a surface in the same plane as one surface of said substrate, and where the impurity ions were ionically implanted through said insulating layer; d. a pair of source and drain regions, the first of which is positioned entirely within said ionically implanted pocket and is of N-type conductivity and the second pair is positioned within that part of said semiconducting substrate entirely without said pocket and is of P-type conductivity; e. a pair of self-registered metallic gate layers located on said insulating layer; and f. contacts extending from said gate layers and said source and drain regions.