US3854059A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flip-flop circuit
Assignee: Hitachi Ltd
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Filing: 1972-11-20
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Granted: 1974-12-10
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Expires: 1992-11-20
Abstract
Abstract A flip-flop circuit formed of a combination of field effect transistors and in which input signals are controlled in the normal logic system by clock pulses of low level. A quasi-static operation is possible. A clock drive of the field effect transistors for loads is also possible.
Inventors
- 👤 K Nomiya
- 👤 H Kawagoe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:35
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356069; H03K3/356078; H03K3/356017; H03K3/356026
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
251 words
A flip-flop circuit comprising a first field effect transistor having a drain connected through first resistance means to a DC power source, a second field effect transistor having a drain connected through second resistance means to said DC power source, the gate of said first field effect transistor being connected to the drain of said second field effect transistor, a third field effect transistor, the gate of said second field effect transistor being connected to said drain of said first field effect transistor through said third field effect transistor, first synchronizing means connected to the gate of said third field effect transistor for applying a first clock pulse signal thereto which renders said third field effect transistor periodically conductive, fourth and fifth field effect transistors connected in parallel, the drains of said fourth and fifth field effect transistors being connected to the source of said first field effect transistor and the sources thereof being grounded, the gate of said fourth field effect transistor being connected to an input signal source, a sixth field effect transistor having a drain connected to the source of said second field effect transistor, the source of said sixth field effect transistor being grounded, and second synchronizing means connected to the gates of said fifth and sixth field effect transistors for applying a second clock pulse signal thereto which renders said fifth and sixth field effect transistors nonconductive when said third field effect transistor is conductive and an input signal is received from said input signal source.
Claim 2
Dependent Claim
251 words
A flip-flop circuit comprising a first field effect transistor having a drain connected through first resistance means to a DC power source, a second field effect transistor having a drain connected through second resistance means to said DC power source, the gate of said first field effect transistor being connected to the drain of said second field effect transistor, a third field effect transistor, the gate of said second field effect transistor being connected to said drain of said first field effect transistor through said third field effect transistor, first synchronizing means connected to the gate of said third field effect transistor for applying a first clock pulse signal thereto which renders said third field effect transistor periodically conductive, fourth and fifth field effect transistors connected in parallel, the drains of said fourth and fifth field effect transistors being connected to the source of said first field effect transistor and the sources thereof being grounded, the gate of said fourth field effect transistor being connected to an input signal source, a sixth field effect transistor having a drain connected to the source of said second field effect transistor, the source of said sixth field effect transistor being grounded, and second synchronizing means connected to the gates of said fifth and sixth field effect transistors for applying a second clock pulse signal thereto which renders said fifth and sixth field effect transistors nonconductive when said third field effect transistor is conductive and an input signal is received from said input signal source.
Claim 3
Dependent Claim
22 words
A flip-flop ciRcuit according to claim 1, wherein said first and second resistance means are seventh and eighth field effect transistors, respectively.
Claim 4
Dependent Claim
26 words
A flip-flop circuit according to claim 1, wherein said input signal source and said second synchronizing signal source provide signals at substantially the same voltage levels.
Claim 5
Dependent Claim
41 words
A semiconductor device according to claim 1, wherein said drain of said second field effect transistor is connected to one of the source or drain of a ninth field effect transistor whose gate is connected to a third synchronizing signal source.
Claim 6
Dependent Claim
124 words
A flip-flop circuit according to claim 2, wherein the source, drain and gate of said seventh field effect transistor are respectively connected to said drain of said first field effect transistor, said DC power source means and said first synchronizing means, and wherein the source, drain and gate of said eighth field effect transistor are respectively connected to said drain of said second field effect transistor, said DC power source and said first synchronizing means, and further including a tenth field effect transistor having a gate connected to a third synchronizing means for applying a third clock pulse signal thereto which renders said tenth field effect transistor periodically conductive, said tenth field effect transistor being connected in parallel with said eighth field effect transistor.
Claim 7
Dependent Claim
265 words
A flip-flop circuit comprising a first field effect transistor having a drain connected through first resistance means to a DC power source, a second field effect transistor having a drain connected through second resistance means to said DC power source, the gate of said first field effect transistor being connected to the drain of said second field effect transistor, a third field effect transistor, the gate of said second field effect transistor being connected to said drain of said first field effect transistor through said third field effect transistor, first synchronizing means connected to the gate of said third field effect transistor for applying a first clock pulse signal thereto which renders said third field effect transistor periodically conductive, fourth and fifth field effect transistors connected in parallel, the drains of said fourth and fifth field effect transistors being connected to the source of said first field effect transistor and the sources thereof being grounded, the gate of said fourth field effect transistor being connected to a first control signal source, sixth and seventh field effect transistors having drains connected to the source of said second field effect transistor and the sources thereof being grounded, the gate of said seventh field effect transistor being connected to a second control signal source, and second synchronizing means connected to the gates of said fifth and sixth field effect transistors for applying a second clock pulse signal thereto which renders said fifth and sixth field transistors nonconductive when said third field effect transistor is conductive and a first control signal is received from said first control signal source.
Claim 8
Dependent Claim
265 words
A flip-flop circuit comprising a first field effect transistor having a drain connected through first resistance means to a DC power source, a second field effect transistor having a drain connected through second resistance means to said DC power source, the gate of said first field effect transistor being connected to the drain of said second field effect transistor, a third field effect transistor, the gate of said second field effect transistor being connected to said drain of said first field effect transistor through said third field effect transistor, first synchronizing means connected to the gate of said third field effect transistor for applying a first clock pulse signal thereto which renders said third field effect transistor periodically conductive, fourth and fifth field effect transistors connected in parallel, the drains of said fourth and fifth field effect transistors being connected to the source of said first field effect transistor and the sources thereof being grounded, the gate of said fourth field effect transistor being connected to a first control signal source, sixth and seventh field effect transistors having drains connected to the source of said second field effect transistor and the sources thereof being grounded, the gate of said seventh field effect transistor being connected to a second control signal source, and second synchronizing means connected to the gates of said fifth and sixth field effect transistors for applying a second clock pulse signal thereto which renders said fifth and sixth field transistors nonconductive when said third field effect transistor is conductive and a first control signal is received from said first control signal source.
Claim 9
Dependent Claim
22 words
A flip-flop circuit according to claim 6, wherein said first and second resistance means are eighth and ninth field effect transistors, respectively.
Claim 10
Dependent Claim
27 words
A flip-flop circuit according to claim 6, wherein said first control signal source and said second synchronizing means provide respective signals at substantially the same voltage levels.
Claim 11
Dependent Claim
59 words
A semiconductor device according to claim 6, wherein said drain of said second field effect transistor is connected to one of the source or drain of a tenth field effect transistor, third synchronizing means for applying a third clock pulse signal to the gate of said tenth field effect transistor which renders said tenth field effect transistor periodically conductive.
Claim 12
Dependent Claim
108 words
A flip-flop circuit according to claim 7, wherein the source, drain and gate of said eighth field effect transistor are respectively connected to said drain of said first field effect transistor, said DC power source and a said first synchronizing means, and wherein the source, drain and gate of said ninth field effect transistor are respectively connected to said drain of said second field effect transistor, said DC power source and said first synchronizing means source, and further including an eleventh field effect transistor having a gate connected to said third synchronizing means, which eleventh field effect transistor is connected in parallel with said ninth field effect transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-09 | 1978-06-10 | 1978-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-09 | 1982-06-10 | 1982-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-09 | 1986-06-10 | 1986-12-10 | $7700.00 | Window Closed / Lapsed |