Patent US3852673A successfully refreshed from Google Patents.
US3852673A
Expired / Lapsed
US
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Method and circuit arrangement for producing and transmitting electrical reference pulses
Assignee: Carl Schenck AG
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Filing: 1972-05-05
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Granted: 1974-12-03
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Expires: 1992-05-05
Abstract
Abstract The present circuit arrangement is, for example, useful for producing reference signals in response to the rotation of a body such as a wheel or rotor to be balanced. Source signals are produced in response to the rotation of said body. Circuit means are provided for handling and comparing the source signals in such a manner that the reference signals are provided at an output terminal in response to the occurrence of the center of a source signal or in response to the maximum of a source signal. The transmittal may also be controlled in response to the center and the maximum of a source signal.
Inventors
- 👤 V Guyot
- 👤 P Holdinghausen
- 👤 M Mueller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:36
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153; H03K5/1532; G; G01; G01M; G01M1/00; G01M1/14; G01M1/16; G01M1/22
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
271 words
A circuit arrangement for producing electrical reference pulse signals having timed relationships to the pulses of a sequence of pulses and transmitting such signals to an output terminal, comprising a pulse source signal generator, signal integrating means having an input and an output, first circuit means operatively arranged for supplying source signals produced by said source signal generator to the input of said signal integrating means, signal amplitude storage means, second circuit means for connecting said signal storage means to the output of said signal integrating means, comparator means, third circuit means for connecting said comparator means to said signal storage means and to said signal integrating means, said comparator being further connected to said output terminal, timing means having an input connected to said source signal generator, said timing means further having output means connected to said signal integrating means and to said signal storage means, whereby a signal value at the output of said integrator means is transferred to said signal storage means in response to an end of a given pulse signal signified by said timing means, whereupon the content of said signal integrating means is erased also in response to said timing means, and wherein a predetermined amplitude portion of a signal stored in said signal storage means is compared in said comparator means with a signal appearing at the output of said signal integrating means as a result of the next pulse signal following said given pulse signal, whereby said electrical reference pulse signals are transmitted to said output terminal in response to the center of the pulse source signals produced by said source signal generator.
Claim 2
Dependent Claim
271 words
A circuit arrangement for producing electrical reference pulse signals having timed relationships to the pulses of a sequence of pulses and transmitting such signals to an output terminal, comprising a pulse source signal generator, signal integrating means having an input and an output, first circuit means operatively arranged for supplying source signals produced by said source signal generator to the input of said signal integrating means, signal amplitude storage means, second circuit means for connecting said signal storage means to the output of said signal integrating means, comparator means, third circuit means for connecting said comparator means to said signal storage means and to said signal integrating means, said comparator being further connected to said output terminal, timing means having an input connected to said source signal generator, said timing means further having output means connected to said signal integrating means and to said signal storage means, whereby a signal value at the output of said integrator means is transferred to said signal storage means in response to an end of a given pulse signal signified by said timing means, whereupon the content of said signal integrating means is erased also in response to said timing means, and wherein a predetermined amplitude portion of a signal stored in said signal storage means is compared in said comparator means with a signal appearing at the output of said signal integrating means as a result of the next pulse signal following said given pulse signal, whereby said electrical reference pulse signals are transmitted to said output terminal in response to the center of the pulse source signals produced by said source signal generator.
Claim 3
Dependent Claim
37 words
The circuit arrangement according to claim 1, wherein said first circuit means comprise a light source and a photocell for sensing said source signal generator, and rectifier means for connecting the photocell to said integrating circuit means.
Claim 4
Dependent Claim
25 words
The circuit arrangement according to claim 2, further comprising variable resistor means interposed between said rectifier means and the input of said signal integrating means.
Claim 5
Dependent Claim
65 words
The circuit arrangement according to claim 1, wherein said integrating circuit means and said signal storage means each comprise controllable circuit members connected to said timing means, said comparator means comprising first impedance means connected to said signal storage means and second impedance means connected to the output of said signal integrating means, said first and second impedance means being connected to said output terminal.
Claim 6
Dependent Claim
39 words
The circuit arrangement according to claim 4, further comprising amplifier means interposed between said first and second impedance means and said output terminal, and potentiometer means connected to said first and second impedance means and to said amplifier means.
Claim 7
Dependent Claim
195 words
A circuit arrangement for producing electrical reference signals having timed relationships to the pulses of a sequence of pulses and transmitting such reference signals to an output terminal, comprising a pulse source signal generator, first and second signal integrating means, a frequency divider connected to said source signal generator, first circuit means responsive to said frequency divider and coupled to alternatively connect said pulse source signal generator to said first and second signal integrating means in response to sequential pulses from said pulse source signal generator, first and second control means for said respective signal integrating means, second circuit means also responsive to said frequency divider and connected to said first and second control means for alternately actuating said first and second control means, signal comparator means, third circuit means also responsive to said frequency divider for connecting said first and second signal integrating means to said signal comparator means, whereby a predetermined portion of the amplitude of a preceding signal is compared with a next following signal amplitude and whereby the transmittal of the reference signal is controlled in response to the center of the pulse source signals produced by said source signal generator.
Claim 8
Dependent Claim
195 words
A circuit arrangement for producing electrical reference signals having timed relationships to the pulses of a sequence of pulses and transmitting such reference signals to an output terminal, comprising a pulse source signal generator, first and second signal integrating means, a frequency divider connected to said source signal generator, first circuit means responsive to said frequency divider and coupled to alternatively connect said pulse source signal generator to said first and second signal integrating means in response to sequential pulses from said pulse source signal generator, first and second control means for said respective signal integrating means, second circuit means also responsive to said frequency divider and connected to said first and second control means for alternately actuating said first and second control means, signal comparator means, third circuit means also responsive to said frequency divider for connecting said first and second signal integrating means to said signal comparator means, whereby a predetermined portion of the amplitude of a preceding signal is compared with a next following signal amplitude and whereby the transmittal of the reference signal is controlled in response to the center of the pulse source signals produced by said source signal generator.
Claim 9
Dependent Claim
37 words
The circuit arrangement according to claim 6, wherein said first circuit means comprise a rectifier and a switching means connected in series and alternately between the source signal generator and the first and second signal integrating means.
Claim 10
Dependent Claim
28 words
The circuit arrangement according to claim 6, wherein said second circuit means are arranged for alternately connecting said first and second control means to said source signal generator.
Claim 11
Dependent Claim
28 words
The circuit arrangement according to claim 6, wherein said first, second, and third circuit means each comprise switching means for performing a single pole double throw switching function.
Claim 12
Dependent Claim
266 words
A circuit arrangement for producing electrical reference signals having timed relationships to the pulses of a sequence of pulses and transmitting such reference signals to an output terminal, comprising a rectangular pulse source signal generator, a counting pulse generator, a gate circuit having one input connected to said source signal generator and another input connected to said counting pulse generator, a digital counter having an input connected to said gate circuit, said gate circuit being opened by the begin of a source signal produced by said source signal generator whereby counting pulses generated by said counting pulse generator are transmitted through said gate into said digital counter in response to the leading edge of said first source signal, digital signal storage means connected to said digital counter, signal comparing means connected to said digital counter and to said digital signal storage means, means for connecting said signal comparing means to said output terminal, timing means connected to said source signal generator, to said digital counter and to said digital signal storage means, whereby the count of said digital signal counter is transmitted into the digital signal storage means in response to the trailing edge of said source signal, whereby the digital counter is simultaneously reset, and whereby signal values counted in response to the next source signal are compared in said signal comparing means with a predetermined portion of a value stored in said signal storage means so that a reference pulse is produced at said output terminal in response to equality ascertained by said signal comparing means at the center of a pulse source signal.
Claim 13
Dependent Claim
266 words
A circuit arrangement for producing electrical reference signals having timed relationships to the pulses of a sequence of pulses and transmitting such reference signals to an output terminal, comprising a rectangular pulse source signal generator, a counting pulse generator, a gate circuit having one input connected to said source signal generator and another input connected to said counting pulse generator, a digital counter having an input connected to said gate circuit, said gate circuit being opened by the begin of a source signal produced by said source signal generator whereby counting pulses generated by said counting pulse generator are transmitted through said gate into said digital counter in response to the leading edge of said first source signal, digital signal storage means connected to said digital counter, signal comparing means connected to said digital counter and to said digital signal storage means, means for connecting said signal comparing means to said output terminal, timing means connected to said source signal generator, to said digital counter and to said digital signal storage means, whereby the count of said digital signal counter is transmitted into the digital signal storage means in response to the trailing edge of said source signal, whereby the digital counter is simultaneously reset, and whereby signal values counted in response to the next source signal are compared in said signal comparing means with a predetermined portion of a value stored in said signal storage means so that a reference pulse is produced at said output terminal in response to equality ascertained by said signal comparing means at the center of a pulse source signal.
Claim 14
Dependent Claim
36 words
The circuit arrangement according to claim 10, wherein said digital signal storage means comprise a second digital counter which counts reversely, said second digital counter being connected to said gate and to said first digital counter.
Claim 15
Dependent Claim
20 words
The circuit arrangement according to claim 11, wherein said counters and storage means operate in accordance with a binary code.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-02 | 1978-06-03 | 1978-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-02 | 1982-06-03 | 1982-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-02 | 1986-06-03 | 1986-12-03 | $7700.00 | Window Closed / Lapsed |