Bistable logic circuits utilizing a charge stored during a clock pulse to change the operating state on the trailing edge of the clock pulse

Claim 2

A bistable circuit including in combination a first flip-flop section having a first operating condition and a second operating condition and operable to produce a signal at a first output terminal indicative of the operating condition, a second flip-flop section having a first operating condition and a second operating condition and operable to produce a signal at a second output terminal indicative of the operating condition, a first feedback connection from the first output terminal to the input of the second flip-flop section tending to cause the second flip-flop section to operate in the second operating condition when the first flip-flop section is in the first operating condition, a second feedback connection from the second output terminal to the input of the first flip-flop section tending to cause the first flip-flop section to operate in the second operating condition when the second flip-flop section is in the first operating condition; an input signal terminal, a steering circuit having a first section and a second section, a first input circuit means in the first section of the steering circuit operable to produce a signal at its output connection during the occurrence of a predetermined combination of concurrent signals at a first plurality of input terminals, the second output terminal of said second flip-flop section being connected to one of said first plurality of input terminals and said input signal terminal being connected to another of said first plurality of input terminals whereby in order for said first input circuit means to produce a signal at its output connection the second flip-flop section must be in the first operating condition and an input signal must be present at said input signal terminal, a first charge storage device, means in said first section of the steering circuit connected to the output connection of the first input circuit means and to the first charge storage device and operable to charge the first charge storage device in response to the presence of a signal at the output connection of the first input circuit means, switching means in said first section of the steering circuit connected to the first charge storage device, the input signal terminal, and the input of the first flip-flop section, said switching means being biased to a high impedance condition during the presence of a signal at the input signal terminal and being operable to switch the first flip-flop section from the second operating condition to the first operating condition in response to a charge in the first charge storage device and to termination of the signal at said input signal terminal, a second input circuit means in the second section of the steering circuit operable to produce a signal at its output connection during the occurrence of a predetermined combination of concurrent signals at a second plurality of input terminals, the first output terminal of said first flip-flop section being connected to one of said second plurality of input terminals and said input signal terminal being connected to another of said second plurality of input terminals whereby in order for said second input circuit means to produce a signal at its output connection the first flip-flop section must be in the first operating condition and an input signal must be present at said input signal terminal, a second charge storage device, means in said second section of the steering circuit connected to the output connection of the second input circuit means and to the second charge storage device and operable to charge the second charge storage device in response to the presence of a signal at the output connectiOn of the second input circuit means, and switching means in said second section of the steering circuit connected to the second charge storage device, the input signal terminal, and the input of the second flip-flop section, said switching means being biased to a high impedance condition during the presence of a signal at the input signal terminal and being operable to switch the second flip-flop section from the second operating condition to the first operating condition in response to a charge in the second charge storage device and to termination of the signal at said input signal terminal.

Claim 3

A bistable circuit as in claim 1 including discharge means connected to the first charge storage device and to the second section of the steering circuit and operable to discharge the first charge storage device while a charge is being stored in the second charge storage device, and discharge means connected to the second charge storage device and to the first section of the steering circuit and operable to discharge the second charge storage device while a charge is being stored in the first charge storage device.

Claim 4

A bistable circuit including in combination a first flip-flop section having a first operating condition and a second operating condition and operable to produce a signal at a first output terminal indicative of the operating condition, a second flip-flop section having a first operating condition and a second operating condition and operable to produce a signal at a second output terminal indicative of the operating condition, a first feedback connection from the first output terminal to the input of the second flip-flop section tending to cause the second flip-flop section to operate in the second operating condition when the first flip-flop section is in the first operating condition, a second feedback connection from the second output terminal to the input of the first flip-flop section tending to cause the first flip-flop section to operate in the second operating condition when the second flip-flop section is in the first operating condition, an input signal terminal, a steering circuit having a first section and a second section, a first input circuit means in the first section of the steering circuit operable to produce a signal at its output connection during the occurrence of a predetermined combination of concurrent signals at a first plurality of input terminals, one of said first plurality of input terminals being connected to the second output terminal of said second flip-flop section, another of said first plurality of input terminals being connected to the input signal terminal, and the remainder of said first plurality of input terminals being connected to information input terminals whereby in order for said first input circuit means to produce a signal at its output connection the second flip-flop section must be in the first operating condition, an input signal must be present at the input signal terminal, and information signals must be present at the information input terminals, a first charge storage device, means in said first section of the steering circuit connected to the output connection of the first input circuit means and to the first charge storage device and operable to charge the first charge storage device in response to the presence of a signal at the output connection of the first input circuit means, switching means in said first section of the steering circuit connected to the first charge storage device, the input signal terminal, and the input of the first flip-flop section, said switching means being biased to a high impedance condition during the presence of a signal at the input signal terminal and being operable to switch the first flip-flop section from the second operating condition to the first operating condition in response to a charge in the first charge storage device and to termination of the signal at said input signal termInal, a second input circuit means in the second section of the steering circuit operable to produce a signal at its output connection during the occurrence of a predetermined combination of concurrent signals at a second plurality of input terminals, one of said second plurality of input terminals being connected to the first output terminal of said first flip-flop section, another of said second plurality of input terminals being connected to the input signal terminal, and the remainder of said second plurality of input terminals being connected to information input terminals whereby in order for said second input circuit means to produce a signal at its output connection the first flip-flop section must be in the first operating condition, and input signal must be present at the input signal terminal, and information signals must be present at the information input terminals, a second charge storage device, means in said second section of the steering circuit connected to the output connection of the second input circuit means and to the second charge storage device and operable to charge the second charge storage device in response to the presence of a signal at the output connection of the second input circuit means, and switching means in said second section of the steering circuit connected to the second charge storage device, the input signal terminal, and the input of the second flip-flop section, said switching means being biased to a high impedance condition during the presence of a signal at the input signal terminal and being operable to switch the second flip-flop section from the second operating condition to the first operating condition in response to a charge in the second charge storage device and to termination of the signal at said input signal terminal.

Claim 5

A bistable circuit including in combination a first flip-flop section having a first operating condition and a second operating condition and operable to produce a signal at a first output terminal indicative of the operating condition, a second flip-flop section having a first operating condition and a second operating condition and operable to produce a signal at a second output terminal indicative of the operating condition, a first feedback connection from the first output terminal to the input of the second flip-flop section tending to cause the second flip-flop section to operate in the second operating condition when the first flip-flop section is in the first operating condition, a second feedback connection from the second output terminal to the input of the first flip-flop section tending to cause the first flip-flop section to operate in the second operating condition when the second flip-flop section is in the first operating condition, an input signal terminal, a steering circuit having a first section and a second section, a first input circuit means in the first section of the steering circuit operable to produce a signal at its output connection during the occurrence of a predetermined combination of concurrent signals at a first plurality of input terminals, one of said first plurality of input terminals being connected to the second output terminal of said second flip-flop section, another of said first plurality of input terminals being connected to the input signal terminal, and the remainder of said first plurality of input terminals being connected to information input terminals whereby in order for said first input circuit means to produce a signal at its output connection the second flip-flop section must be in the first operating condition, an input signal must be present at the input signal terminal, and information signals must be present at the information input terminals, a first charge storage device, means in said first section of the steering circuit connected to the output connection of the first input circuit means and to the first charge storage device and operable to charge the first charge storage device in response to the presence of a signal at the output connection of the first input circuit means, switching means in said first section of the steering circuit connected to the first charge storage device, the input signal terminal, and the input of the first flip-flop section, said switching means being biased to a high impedance condition during the presence of a signal at the input signal terminal and being operable to switch the first flip-flop section from the second operating condition to the first operating condition in response to a charge in the first charge storage device and to termination of the signal at said input signal termInal, a second input circuit means in the second section of the steering circuit operable to produce a signal at its output connection during the occurrence of a predetermined combination of concurrent signals at a second plurality of input terminals, one of said second plurality of input terminals being connected to the first output terminal of said first flip-flop section, another of said second plurality of input terminals being connected to the input signal terminal, and the remainder of said second plurality of input terminals being connected to information input terminals whereby in order for said second input circuit means to produce a signal at its output connection the first flip-flop section must be in the first operating condition, and input signal must be present at the input signal terminal, and information signals must be present at the information input terminals, a second charge storage device, means in said second section of the steering circuit connected to the output connection of the second input circuit means and to the second charge storage device and operable to charge the second charge storage device in response to the presence of a signal at the output connection of the second input circuit means, and switching means in said second section of the steering circuit connected to the second charge storage device, the input signal terminal, and the input of the second flip-flop section, said switching means being biased to a high impedance condition during the presence of a signal at the input signal terminal and being operable to switch the second flip-flop section from the second operating condition to the first operating condition in response to a charge in the second charge storage device and to termination of the signal at said input signal terminal.

Claim 6

A bistable circuit including in combination a first flip-flop section having a first operating condition during which a first predetermined voltage level is produced at a first output terminal and having a second operating condition during which a second predetermined voltage level is produced at the first output terminal, said first flip-flop section having a first input connection means thereto and being operable in the second operating condition during the presence of the first predetermined voltage level at said first input connection means, a second flip-flop section having a first operating condition during which the first predetermined voltage level is produced at a second output terminal and having a second operating condition during which the second predetermined voltage level is produced at the second output terminal, said second flip-flop section having a second input connection means thereto and being operable in the second operating condition during the presence of the first predetermined voltage level at said second input connection means, a first feedback connection from the first output terminal to the second input connection means whereby when said first flip-flop section is in the first operating condition the second flip-flop section is in the second operating condition, a second feedback connection from the second output terminal to the first input connection means whereby when said second flip-flop section is in the first operating condition the first flip-flop section is in the second operating condition, an input signal terminal, a steering circuit having a first section and a second section, a first input circuit means in the first section of the steering circuit operable to produce a signal at its output connection during the concurrent occurrence of the first predetermined voltage level at first and second input terminals, the second output terminal of said second flip-flop section being connected to the first input terminal of the first input circuit means and said input signal terminal being connected to the second input terminal of the first input circuit means whereby in order for said firsT input circuit means to produce a signal at its output connection the second flip-flop section must be in the first operating condition and the first predetermined voltage level must be present at the input signal terminal, a first charge storage device, a first charging transistor connected between the first charge storage device and a source of voltage and operable when biased to low impedance condition to permit the first charge storage device to be charged by the source of voltage, means connecting said first charging transistor to the output connection of the first input circuit means, said means being operable to bias the first charging transistor to a high impedance condition in the absence of a signal at the output connection and to bias the first charging transistor to a low impedance condition in response to a signal at the output connection whereby the first charge storage device is charged by the source of voltage, a first switching transistor connected to the first input connection means of the first flip-flop section and operable when biased to a low impedance condition to switch the first flip-flop section from the second operating condition to the first operating condition, means connecting said first switching transistor to the first charge storage device and to the input signal terminal, said means being operable to bias the first switching transistor to a high impedance condition by the presence of the first predetermined voltage level at the input signal terminal and by the absence of a charge in the first charge storage device and being operable to bias the first switching transistor to a low impedance condition by the presence of a charge in the first charge storage device when the first predetermined voltage level is not present at the input signal terminal whereby the first flip-flop section is switched from the second operating condition to the first operating condition, a second input circuit means in the second section of the steering circuit operable to produce a signal at its output connection during the concurrent occurrence of the first predetermined voltage level at first and second input terminals, the first output terminal of said first flip-flop section being connected to the first input terminal of the second input circuit means and said input signal terminal being connected to the second input terminal of the second input circuit means whereby in order for said second input circuit means to produce a signal at its output connection the first flip-flop section must be in the first operating condition and the first predetermined voltage level must be present at the input signal terminal, a second charge storage device, a second charging transistor connected between the second charge storage device and a source of voltage and operable when biased to a low impedance condition to permit the second charge storage device to be charged by the source of voltage, means connecting said second charging transistor to the output connection of the second input circuit means, said means being operable to bias the second charging transistor to a high impedance condition in the absence of a signal at the output connection and to bias the second charging transistor to a low impedance condition in response to a signal at the output connection whereby the second charge storage device is charged by the source of voltage, a second switching transistor connected to the second input connection means of the second flip-flop section and operable when biased to a low impedance condition to switch the second flip-flop section from the second operating condition to the first operating condition, and means connecting said second switching transistor to the second charge storage device and to the input signal terminal, said means being operable to bias the second switching transistor to a high impedance condition by the presence of the first predetermined voltage level at the input signal terminal and by the aBsence of a charge in the second charge storage device, and being operable to bias the second switching transistor to a low impedance condition by the presence of a charge in the second charge storage device when the first predetermined voltage level is not present at the input signal terminal whereby the second flip-flop section is switched from the second operating condition to the first operating condition.

Claim 7

A bistable circuit including in combination a first flip-flop section having a first operating condition during which a first predetermined voltage level is produced at a first output terminal and having a second operating condition during which a second predetermined voltage level is produced at the first output terminal, said first flip-flop section having a first input connection means thereto and being operable in the second operating condition during the presence of the first predetermined voltage level at said first input connection means, a second flip-flop section having a first operating condition during which the first predetermined voltage level is produced at a second output terminal and having a second operating condition during which the second predetermined voltage level is produced at the second output terminal, said second flip-flop section having a second input connection means thereto and being operable in the second operating condition during the presence of the first predetermined voltage level at said second input connection means, a first feedback connection from the first output terminal to the second input connection means whereby when said first flip-flop section is in the first operating condition the second flip-flop section is in the second operating condition, a second feedback connection from the second output terminal to the first input connection means whereby when said second flip-flop section is in the first operating condition the first flip-flop section is in the second operating condition, an input signal terminal, a steering circuit having a first section and a second section, a first input circuit means in the first section of the steering circuit operable to produce a signal at its output connection during the concurrent occurrence of the first predetermined voltage level at first and second input terminals, the second output terminal of said second flip-flop section being connected to the first input terminal of the first input circuit means and said input signal terminal being connected to the second input terminal of the first input circuit means whereby in order for said firsT input circuit means to produce a signal at its output connection the second flip-flop section must be in the first operating condition and the first predetermined voltage level must be present at the input signal terminal, a first charge storage device, a first charging transistor connected between the first charge storage device and a source of voltage and operable when biased to low impedance condition to permit the first charge storage device to be charged by the source of voltage, means connecting said first charging transistor to the output connection of the first input circuit means, said means being operable to bias the first charging transistor to a high impedance condition in the absence of a signal at the output connection and to bias the first charging transistor to a low impedance condition in response to a signal at the output connection whereby the first charge storage device is charged by the source of voltage, a first switching transistor connected to the first input connection means of the first flip-flop section and operable when biased to a low impedance condition to switch the first flip-flop section from the second operating condition to the first operating condition, means connecting said first switching transistor to the first charge storage device and to the input signal terminal, said means being operable to bias the first switching transistor to a high impedance condition by the presence of the first predetermined voltage level at the input signal terminal and by the absence of a charge in the first charge storage device and being operable to bias the first switching transistor to a low impedance condition by the presence of a charge in the first charge storage device when the first predetermined voltage level is not present at the input signal terminal whereby the first flip-flop section is switched from the second operating condition to the first operating condition, a second input circuit means in the second section of the steering circuit operable to produce a signal at its output connection during the concurrent occurrence of the first predetermined voltage level at first and second input terminals, the first output terminal of said first flip-flop section being connected to the first input terminal of the second input circuit means and said input signal terminal being connected to the second input terminal of the second input circuit means whereby in order for said second input circuit means to produce a signal at its output connection the first flip-flop section must be in the first operating condition and the first predetermined voltage level must be present at the input signal terminal, a second charge storage device, a second charging transistor connected between the second charge storage device and a source of voltage and operable when biased to a low impedance condition to permit the second charge storage device to be charged by the source of voltage, means connecting said second charging transistor to the output connection of the second input circuit means, said means being operable to bias the second charging transistor to a high impedance condition in the absence of a signal at the output connection and to bias the second charging transistor to a low impedance condition in response to a signal at the output connection whereby the second charge storage device is charged by the source of voltage, a second switching transistor connected to the second input connection means of the second flip-flop section and operable when biased to a low impedance condition to switch the second flip-flop section from the second operating condition to the first operating condition, and means connecting said second switching transistor to the second charge storage device and to the input signal terminal, said means being operable to bias the second switching transistor to a high impedance condition by the presence of the first predetermined voltage level at the input signal terminal and by the aBsence of a charge in the second charge storage device, and being operable to bias the second switching transistor to a low impedance condition by the presence of a charge in the second charge storage device when the first predetermined voltage level is not present at the input signal terminal whereby the second flip-flop section is switched from the second operating condition to the first operating condition.

Claim 8

A bistable circuit as in claim 4 including a first discharging transistor connected in shunt across said first charge storage device and operable when biased to a low impedance condition to permit discharge of the first charge storage device, means connecting said first discharging transistor to the second section of the steering circuit, said means being operable to bias the first discharging transistor to a high impedance condition in the absence of a charge in the second charge storage device, and being operable to bias the first discharging transistor to a low impedance condition by the presence of a charge in the second charge storage device whereby the first charge storage device is discharged, a second discharging transistor connected in shunt across said second charge storage device and operable when biased to a low impedance condition to permit discharge of the second charge storage device, and means connecting said second discharging transistor to the first section of the steering circuit, said means being operable to bias the second discharging transistor to a high impedance condition in the absence of a charge in the first charge storage device, and being operable to bias the second discharging transistor to a low impedance condition by the presence of a charge in the first charge storage device whereby the second charge storage device is discharged.

Claim 9

A bistable circuit including in combination a first flip-flop section having a first operating condition during which a first predetermined voltage level is produced at a first output terminal and having a second operating condition during which a second predetermined voltage level is produced at the first output terminal, said first flip-flop section having a first input connection means thereto and being operable in the second operating condition during the presence of the first predetermined voltage level at said first input connection means, a second flip-flop section having a first operating condition during which the first predetermined voltage level is produced at a second output terminal and having a second operating condition during which the second voltage level is produced at the second output terminal, said second flip-flop section having a second input connection means thereto and being operable in the second operating condition during the presence of the first predetermined voltage level at said second input connection means, a first feedback connection from the first output terminal to the second input connection means whereby when said first flip-flop section is in the first operating condition the second flip-flop section is in the second operating condition, a second feedback connection from the second output terminal to the first input connection means whereby when said second flip-flop section is in the first operating condition the first flip-flop section is in the second operating condition, an input signal terminal, a steering circuit having a first section and a second section, a first input circuit means in the first section of the steering circuit operable to produce a signal at its output connection during the concurrent occurrence of the first predetermined voltage level at a first plurality of input terminals, one of said first plurality of input terminals being connected to the second output terminal of said second flip-flop section, another of said first plurality of input terminals being connected to the input signal terminal, and the remainder of said first plurality of input terminals being connecTed to a first set of information input terminals whereby in order for said first input circuit means to produce a signal at its output connection the second flip-Flop section must be in the first operating condition, the first predetermined voltage level must be present at the input signal terminal, and the first predetermined voltage level must be present at each of the first set of information input terminals, a first capacitance, a first charging transistor having its emitter connected to ground through the first capacitance, its collector connected to a source of voltage, and its base connected to the output connection of the first input circuit means, and operable when biased to a low impedance condition to permit the first capacitance to be charged, said first charging transistor being biased to a high impedance condition in the absence of a signal at the output connection of the first input circuit means and being biased to a low impedance condition by the presence of a signal at the output connection of the first input circuit means whereby the first capacitance is charged, a first switching transistor having its emitter connected to the input signal terminal, its collector connected to the first input connection means of the first flip-flop section, nd its base connected to the emitter of the first charging transistor, and operable when biased to a low impedance condition to switch the first flip-flop section from the second operating condition to the first operating condition, said first switching transistor being biased to a high impedance condition by the presence of the first predetermined voltage level at the input signal terminal and by the absence of a charge in the first capacitance and being biased to a low impedance condition by the presence of a charge in the first capacitance when the first predetermined voltage level is not present at the input signal terminal whereby the first flip-flop section is switched from the second operating condition to the first operating condition, a second input circuit means in the second section of the steering circuit operable to produce a signal at its output connection during the concurrent occurrence of the first predetermined voltage level at a second plurality of input terminals, one of said second plurality of input terminals being connected to the first output terminal of said first flip-flop section, another of said second plurality of input terminals being connected to the input signal terminal, and the remainder of said second plurality of input terminals being connected to a second set of information input terminals whereby in order for said second input circuit means to produce a signal at its output connection the first flip-flop section must be in the first operating condition, the first predetermined voltage level must be present at the input signal terminal, and the first predetermined voltage level must be present at each of the second set of information input terminals, a second capacitance, a second charging transistor having its emitter connected to ground through the second capacitance, its collector connected to a source of voltage, and its base connected to the output connection of the second input circuit means, and operable when biased to a low impedance condition to permit the second capacitance to be charged, said second charging transistor being biased to a high impedance condition in the absence of a signal at the output connection of the second input circuit means and being biased to a low impedance condition by the presence of a signal at the output connection of the second input circuit means whereby the second capacitance is charged, and a second switching transistor having its emitter connected to the input signal terminal, its collector connected to the second input connection means of the second flip-flop section, and its base connected to the emitter of the second charging transistor, and operable when biased to a low impedance Condition to switch the second flip-flop section from the second operating condition to the first operating condition, said second switching transistor being biased to a high impedance condition by the presence of the first predetermined voltage level at the input signal terminal and the absence of a charge in the second capacitance and being biased to a low impedance condition by the presence of a charge in the second capacitance when the first predetermined voltage level is not present at the input signal terminal whereby the second flip-flop section is switched from the second operating condition to the first operating condition.

Claim 10

A bistable circuit including in combination a first flip-flop section having a first operating condition during which a first predetermined voltage level is produced at a first output terminal and having a second operating condition during which a second predetermined voltage level is produced at the first output terminal, said first flip-flop section having a first input connection means thereto and being operable in the second operating condition during the presence of the first predetermined voltage level at said first input connection means, a second flip-flop section having a first operating condition during which the first predetermined voltage level is produced at a second output terminal and having a second operating condition during which the second voltage level is produced at the second output terminal, said second flip-flop section having a second input connection means thereto and being operable in the second operating condition during the presence of the first predetermined voltage level at said second input connection means, a first feedback connection from the first output terminal to the second input connection means whereby when said first flip-flop section is in the first operating condition the second flip-flop section is in the second operating condition, a second feedback connection from the second output terminal to the first input connection means whereby when said second flip-flop section is in the first operating condition the first flip-flop section is in the second operating condition, an input signal terminal, a steering circuit having a first section and a second section, a first input circuit means in the first section of the steering circuit operable to produce a signal at its output connection during the concurrent occurrence of the first predetermined voltage level at a first plurality of input terminals, one of said first plurality of input terminals being connected to the second output terminal of said second flip-flop section, another of said first plurality of input terminals being connected to the input signal terminal, and the remainder of said first plurality of input terminals being connecTed to a first set of information input terminals whereby in order for said first input circuit means to produce a signal at its output connection the second flip-Flop section must be in the first operating condition, the first predetermined voltage level must be present at the input signal terminal, and the first predetermined voltage level must be present at each of the first set of information input terminals, a first capacitance, a first charging transistor having its emitter connected to ground through the first capacitance, its collector connected to a source of voltage, and its base connected to the output connection of the first input circuit means, and operable when biased to a low impedance condition to permit the first capacitance to be charged, said first charging transistor being biased to a high impedance condition in the absence of a signal at the output connection of the first input circuit means and being biased to a low impedance condition by the presence of a signal at the output connection of the first input circuit means whereby the first capacitance is charged, a first switching transistor having its emitter connected to the input signal terminal, its collector connected to the first input connection means of the first flip-flop section, nd its base connected to the emitter of the first charging transistor, and operable when biased to a low impedance condition to switch the first flip-flop section from the second operating condition to the first operating condition, said first switching transistor being biased to a high impedance condition by the presence of the first predetermined voltage level at the input signal terminal and by the absence of a charge in the first capacitance and being biased to a low impedance condition by the presence of a charge in the first capacitance when the first predetermined voltage level is not present at the input signal terminal whereby the first flip-flop section is switched from the second operating condition to the first operating condition, a second input circuit means in the second section of the steering circuit operable to produce a signal at its output connection during the concurrent occurrence of the first predetermined voltage level at a second plurality of input terminals, one of said second plurality of input terminals being connected to the first output terminal of said first flip-flop section, another of said second plurality of input terminals being connected to the input signal terminal, and the remainder of said second plurality of input terminals being connected to a second set of information input terminals whereby in order for said second input circuit means to produce a signal at its output connection the first flip-flop section must be in the first operating condition, the first predetermined voltage level must be present at the input signal terminal, and the first predetermined voltage level must be present at each of the second set of information input terminals, a second capacitance, a second charging transistor having its emitter connected to ground through the second capacitance, its collector connected to a source of voltage, and its base connected to the output connection of the second input circuit means, and operable when biased to a low impedance condition to permit the second capacitance to be charged, said second charging transistor being biased to a high impedance condition in the absence of a signal at the output connection of the second input circuit means and being biased to a low impedance condition by the presence of a signal at the output connection of the second input circuit means whereby the second capacitance is charged, and a second switching transistor having its emitter connected to the input signal terminal, its collector connected to the second input connection means of the second flip-flop section, and its base connected to the emitter of the second charging transistor, and operable when biased to a low impedance Condition to switch the second flip-flop section from the second operating condition to the first operating condition, said second switching transistor being biased to a high impedance condition by the presence of the first predetermined voltage level at the input signal terminal and the absence of a charge in the second capacitance and being biased to a low impedance condition by the presence of a charge in the second capacitance when the first predetermined voltage level is not present at the input signal terminal whereby the second flip-flop section is switched from the second operating condition to the first operating condition.

Claim 11

A bistable circuit as in claim 6 including a third input circuit means in the first section of the steering circuit operable to produce a signal at its output connection during the concurrent occurrence of the first predetermined voltage level at a third plurality of input terminals, one of said third plurality of input terminals being connected to the second output terminal of said second flip-Flop section, another of said third plurality of input terminals being connected to the input signal terminal, and the remainder of said third plurality of input terminals being connected to a third set of information input terminals whereby in order for said third input circuit means to produce a signal at its output connection the second flip-flop section must be in the first operating condition, the first predetermined voltage level must be present at the input signal terminal, and the first predetermined voltage level must be present at each of said third set of information input terminals, a third charging transistor having its emitter connected directly to the emitter of the first charging transistor, its collector connected directly to the collector of the first charging transistor, and its base connected to the output connection of the third input circuit means, and operable when biased to a low impedance condition to permit the first capacitance to be charged, said third charging transistor being biased to a high impedance condition in the absence of a signal at the output connection of the third input circuit means and being biased to a low impedance condition by the presence of a signal at the output connection of the third input circuit means whereby the first capacitance is charged, a fourth input circuit means in the second section of the steering circuit operable to produce a signal at its output connection during the concurrent occurrence of the first predetermined voltage level at a fourth plurality of input terminals, one of said fourth plurality of input terminals being connected to the first output terminal of said first flip-flop section, another of said first plurality of input terminals being connected to the input signal terminal, and the remainder of said forth plurality of input terminals being connected to a fourth set of information input terminals whereby in order for said fourth input circuit means to produce a signal at its output connection the first flip-flop section must be in the first operating condition, the first predetermined voltage level must be present at the input signal terminal, and the first predetermined voltage level must be present at each of the fourth set of information input terminals, and a fourth charging transistor having its emitter connected directly to the emitter of the second charging transistor, its collector connected directly to the collector of the second charging transistor, and its base connected to the output connection of the fourth input circuit means, and operable when biased to a low impedance condition to permit the second capacitance to be charged, said fourth charging transistor being biased to a high impedance condition in the absence of a signal at the output connection of the fourth input circuit means and being biased to a low impedance condition by tHe presence of a signal at the output connection of the fourth input circuit means whereby the second capacitance is charged.

Claim 12

A bistable circuit as in claim 6 including a first discharging transistor connected across the first capacitance with its emitter connected to ground, its collector connected to the emitter of the first charging transistor, and its base connected to the emitter of the second charging transistor, and operable when biased to a low impedance condition to permit discharge of the first capacitance, said first discharging transistor being biased to a high impedance condition in the absence of a voltage across the second capacitance and being biased to a low impedance condition by the presence of a voltage across the second capacitance whereby the first capacitance is discharged, and a second discharging transistor connected across the second capacitance with its emitter connected to ground, its collector connected to the emitter of the second charging transistor, and its base connected to the emitter of the first charging transistor, and operable when biased to a low impedance condition to permit discharge of the second capacitance, said second discharging transistor being biased to a high impedance condition in the absence of a voltage across the first capacitance and being biased to low impedance condition by the presence of a voltage across the first capacitance whereby the second capacitance is discharged.

Claim 13

A bistable circuit including in combination a first flip-flop section having a first operating condition and a second operating condition, a second flip-flop section having a first operating condition and a second operating condition, feedback connections between the first and second flip-flop sections for causing the flip-flop sections to operate in different operating conditions, a steering circuit having input connections from the first and second flip-flop sections and output connections to the first and second flip-flop sections, an input signal terminal connected to the steering circuit, a first charge storage device, a second charge storage device, a first charging circuit means connected to the first charge storage device and operable when biased to a low impedance condition to cause a charge to be stored in the first charge storage device, means connecting said first charging circuit means to an input connection and to the input signal terminal, said means being operable to bias the first charging circuit means to a high impedance condition in the absence of an input signal at said input signal terminal and to bias the first charging circuit means to a low impedance condition during the presence of an input signal at said input signal terminal while the second flip-flop section is in the first operating condition and the first flip-flop section is in the second operating condition, a first switching circuit means connected to the first charge storage device, the input signal terminal, and an output connection, said first switching circuit means being biased to a high impedance condition during the presence of an input signal at the input signal terminal and being operable to switch the first flip-flop section from the second operating condition to the first operating condition in response to a charge in the first charge storage device and to termination of the input signal at said input signal terminal, a second charging circuit means connected to the second charge storage device and operable when biased to a low impedance condition to cause a charge to be stored in the second charge storage device, means connecting said second charging circuit means to an input connection and to the input signal terminal, said means being operable to bias the second charging circuit means to a high impedance condition in the absence of an input signal at said input signal terminal and to bias the second charging circuit means to a low impedance condition during the presence of an input signal at said input signal terminal while thE first flip-flop section is in the first operating condition and the second flip-flop section is in the second operating condition, and a second switching circuit means connected to the second charge storage device, the input signal terminal, and an output connection, said second switching circuit means being biased to a high impedance condition during the presence of an input signal at the input signal terminal and being operable to switch the second flip-flop section from the second operating condition to the first operating condition in response to a charge in the second charge storage device and to termination of the input signal at said input signal terminal.

Claim 14

A bistable circuit including in combination a first flip-flop section having a first operating condition and a second operating condition, a second flip-flop section having a first operating condition and a second operating condition, feedback connections between the first and second flip-flop sections for causing the flip-flop sections to operate in different operating conditions, a steering circuit having input connections from the first and second flip-flop sections and output connections to the first and second flip-flop sections, an input signal terminal connected to the steering circuit, a first charge storage device, a second charge storage device, a first charging circuit means connected to the first charge storage device and operable when biased to a low impedance condition to cause a charge to be stored in the first charge storage device, means connecting said first charging circuit means to an input connection and to the input signal terminal, said means being operable to bias the first charging circuit means to a high impedance condition in the absence of an input signal at said input signal terminal and to bias the first charging circuit means to a low impedance condition during the presence of an input signal at said input signal terminal while the second flip-flop section is in the first operating condition and the first flip-flop section is in the second operating condition, a first switching circuit means connected to the first charge storage device, the input signal terminal, and an output connection, said first switching circuit means being biased to a high impedance condition during the presence of an input signal at the input signal terminal and being operable to switch the first flip-flop section from the second operating condition to the first operating condition in response to a charge in the first charge storage device and to termination of the input signal at said input signal terminal, a second charging circuit means connected to the second charge storage device and operable when biased to a low impedance condition to cause a charge to be stored in the second charge storage device, means connecting said second charging circuit means to an input connection and to the input signal terminal, said means being operable to bias the second charging circuit means to a high impedance condition in the absence of an input signal at said input signal terminal and to bias the second charging circuit means to a low impedance condition during the presence of an input signal at said input signal terminal while thE first flip-flop section is in the first operating condition and the second flip-flop section is in the second operating condition, and a second switching circuit means connected to the second charge storage device, the input signal terminal, and an output connection, said second switching circuit means being biased to a high impedance condition during the presence of an input signal at the input signal terminal and being operable to switch the second flip-flop section from the second operating condition to the first operating condition in response to a charge in the second charge storage device and to termination of the input signal at said input signal terminal.

Claim 15

A bistable circuit as in claim 9 including a first discharging circuit means connected to the first charge storage device and operable when biased to a low impedance condition to discharge the first charge storage device, means connecting the first discharging circuit means to the second charging circuit means, said means being operable to bias the first discharging circuit means to a high impedance condition when the second charging circuit means is in a high impedance condition and to bias the first discharging circuit means to a low impedance condition when the second charging circuit means is in a low impedance condition, a second discharging circuit means connected to the second charge storage device and operable when biased to a low impedance condition to discharge the second charge storage device, and means connecting the second discharging circuit means to the first charging circuit means, said means being operable to bias the second discharging circuit means to a high impedance condition when the first charging circuit means is in a high impedance condition and to bias the second discharging circuit means to a low impedance condition when the first charging circuit means is in a low impedance condition.

Claim 16

A bistable circuit including in combination a first flip-flop section having a first operating condition and a second operating condition, a second flip-flop section having a first operating condition and a second operating condition, feedback connections between the first and second flip-flop sections for causing the flip-flop sections to operate in different operating conditions, a steering circuit having input connections from the first and second flip-flop sections and output connections to the first and second flip-flop sections, an input signal terminal connected to the steering circuit, a first charge storage device, a second charge storage device, a first charging transistor connected between the first charge storage device and a first source of reference potential and operable when biased to a low impedance condition to permit the first charge storage device to be charged by the first source of reference potential, means connecting the first charging transistor to one input connection and to the input signal terminal, said means being operable to bias the first charging transistor to a high impedance condition in the absence of an input signal at said input signal terminal and to bias the first charging transistor to the low impedance condition during the presence of an input signal at said input signal terminal while the second flip-flop section is in the first operating condition and the first flip-flop section is in the second operating condition, a first switching transistor connected to one output connection and operable when biased to a low impedance condition to switch the first flip-flop section from the second operating condition to the first operating condition, means connecting the first switching transistor to the first charge storage device and to the input signal terminal, said means being operable to bias the first switching transistor to a high impedance condition during the presence of an input signal at the input signal terminal and by the absence of a charge in the first charge storage deVice and being operable to bias the first switching transistor to a low impedance condition by the presence of a charge in the first charge storage device during the absence of an input signal at the input signal terminal, a second charging transistor connected between the second charge storage device and the first source of reference potential and operable when biased to a low impedance condition to permit the second charge storage device to be charged by the first source of reference potential, means connecting the second charging transistor to the other input connection and to the input signal terminal, said means being operable to bias the second charging transistor to a high impedance condition in the absence of an input signal at said input signal terminal and to bias the second charging transistor to the low impedance condition during the presence of an input signal at said input signal terminal while the first flip-flop section is in the first operating condition and the second flip-flop section is in the second operating condition, a second switching transistor connected to the other output connection and operable when biased to a low impedance condition to switch the second flip-flop section from the second operating condition to the first operating condition, and means connecting the second switching transistor to the second charge storage device and to the input signal terminal, said means being operable to bias the second switching transistor to a high impedance condition during the presence of an input signal at the input signal terminal and by the absence of a charge in the second charge storage device and being operable to bias the second switching transistor to a low impedance condition by the presence of a charge in the second charge storage device during the absence of an input signal at the input signal terminal.

Claim 17

A bistable circuit including in combination a first flip-flop section having a first operating condition and a second operating condition, a second flip-flop section having a first operating condition and a second operating condition, feedback connections between the first and second flip-flop sections for causing the flip-flop sections to operate in different operating conditions, a steering circuit having input connections from the first and second flip-flop sections and output connections to the first and second flip-flop sections, an input signal terminal connected to the steering circuit, a first charge storage device, a second charge storage device, a first charging transistor connected between the first charge storage device and a first source of reference potential and operable when biased to a low impedance condition to permit the first charge storage device to be charged by the first source of reference potential, means connecting the first charging transistor to one input connection and to the input signal terminal, said means being operable to bias the first charging transistor to a high impedance condition in the absence of an input signal at said input signal terminal and to bias the first charging transistor to the low impedance condition during the presence of an input signal at said input signal terminal while the second flip-flop section is in the first operating condition and the first flip-flop section is in the second operating condition, a first switching transistor connected to one output connection and operable when biased to a low impedance condition to switch the first flip-flop section from the second operating condition to the first operating condition, means connecting the first switching transistor to the first charge storage device and to the input signal terminal, said means being operable to bias the first switching transistor to a high impedance condition during the presence of an input signal at the input signal terminal and by the absence of a charge in the first charge storage deVice and being operable to bias the first switching transistor to a low impedance condition by the presence of a charge in the first charge storage device during the absence of an input signal at the input signal terminal, a second charging transistor connected between the second charge storage device and the first source of reference potential and operable when biased to a low impedance condition to permit the second charge storage device to be charged by the first source of reference potential, means connecting the second charging transistor to the other input connection and to the input signal terminal, said means being operable to bias the second charging transistor to a high impedance condition in the absence of an input signal at said input signal terminal and to bias the second charging transistor to the low impedance condition during the presence of an input signal at said input signal terminal while the first flip-flop section is in the first operating condition and the second flip-flop section is in the second operating condition, a second switching transistor connected to the other output connection and operable when biased to a low impedance condition to switch the second flip-flop section from the second operating condition to the first operating condition, and means connecting the second switching transistor to the second charge storage device and to the input signal terminal, said means being operable to bias the second switching transistor to a high impedance condition during the presence of an input signal at the input signal terminal and by the absence of a charge in the second charge storage device and being operable to bias the second switching transistor to a low impedance condition by the presence of a charge in the second charge storage device during the absence of an input signal at the input signal terminal.

Claim 18

A bistable circuit as in claim 11 including a first discharging transistor connected in shunt across said first charge storage device and operable when biased to a low impedance condition to permit discharge of the first charge storage device, means connecting the first discharging transistor to the second charging transistor, said means being operable to bias the first discharging transistor to a high impedance condition when the second charging transistor is in a high impedance condition and to bias the first discharging transistor to a low impedance condition when the second charging transistor is in a low impedance condition, a second discharging transistor connected in shunt across said second charge storage device and operable when biased to a low impedance condition to permit discharge of the second charge storage device, and means connecting the second discharging transistor to the first charging transistor, said means being operable to bias the second discharging transistor to a high impedance condition when the first charging transistor is in a high impedance condition and to bias the second discharging transistor to a low impedance condition when the first charging transistor is in a low impedance condition.

Claim 19

A bistable circuit as in claim 11 wherein said first charge storage device is a first capacitance having one terminal connected to a second source of reference potential, said first charging transistor has its emitter connected to the other terminal of the first capacitance, its collector connected to the first source of reference potential, and its base connected to said means connecting the first charging transistor to one input connection and to the input signal terminal, said first switching transistor has its emitter connected to the input signal terminal, its collector connected to the one output connection, and its base connected to the emitter of the first charging transistor and to said other terminal of the first capacitance, said second charge storage device is a second capacitance having one terminal connected to the second source of reference potEntial, said second charging transistor has its emitter connected to the other terminal of the second capacitance, its collector connected to the first source of reference potential, and its base connected to said means connecting the second charging transistor to the other input connection and to the input signal terminal, and said second switching transistor has its emitter connected to the input signal terminal, its collector connected to the other output connection, and its base connected to the emitter of the second charging transistor and to said other terminal of the second capacitance.

Claim 20

A bistable circuit as in claim 12 wherein said first charge storage device is a first capacitance having one terminal connected to a second source of reference potential, said first charging transistor has its emitter connected to the other terminal of the first capacitance, its collector connected to the first source of reference potential, and its base connected to said means connecting the first charging transistor to one input connection and to the input signal terminal, said first switching transistor has its emitter connected to the input signal terminal, its collector connected to the one output connection, and its base connected to the emitter of the first charging transistor and to said other terminal of the first capacitance, said second charge storage device is a second capacitance having one terminal connected to the second source of reference potential, said second charging transistor has its emitter connected to the other terminal of the second capacitance, its collector connected to the first source of reference potential, and its base connected to said means connecting the second charging transistor to the other input connection and to the input signal terminal, said second switching transistor has its emitter connected to the input signal terminal, its collector connected to the other output connection, and its base connected to the emitter of the second charging transistor and to said other terminal of the second capacitance, said first discharging transistor has its emitter connected to said one terminal of the first capacitance, its collector connected to said other terminal of the first capacitance, and its base connected to the emitter of the second charging transistor, and said second discharging transistor has its emitter connected to said one terminal of the second capacitance, its collector connected to said other terminal of the second capacitance, and its base connected to the emitter of the first charging transistor.

Claim 21

In a steering network having first and second transistors of one conductivity type and each having an input electrode, an output electrode and a common electrode; means for connecting first and second output loads at the output electrodes of the first and second transistors, respectively; a control terminal means; means coupling each common electrode to said control terminal means; first and second capacitor means each connected between the input electrode of a different one of the first and second transistors and a point of reference potential; third and fourth transistors connected to charge the first and second capacitor means, respectively; and means for applying at said control terminal means control signals to render conductive one of the first and second transistors when its associated capacitor means is charged; the improvement comprising: a first circuit coupled to the input electrode of the first transistor and including first signal responsive means selectively operable to provide a low impedance path across said first capacitor means; and a second circuit coupled to the input electrode of the second transistor and including second signal responsive means selectively operable to provide a low impedance path across said second capacitor means.

Claim 22

In a steering network having first and second transistors of one conductivity type and each having an input electrode, an output electrode and a common electrode; means for connecting first and second output loads at the output electrodes of the first and second transistors, respectively; a control terminal means; means coupling each common electrode to said control terminal means; first and second capacitor means each connected between the input electrode of a different one of the first and second transistors and a point of reference potential; third and fourth transistors connected to charge the first and second capacitor means, respectively; and means for applying at said control terminal means control signals to render conductive one of the first and second transistors when its associated capacitor means is charged; the improvement comprising: a first circuit coupled to the input electrode of the first transistor and including first signal responsive means selectively operable to provide a low impedance path across said first capacitor means; and a second circuit coupled to the input electrode of the second transistor and including second signal responsive means selectively operable to provide a low impedance path across said second capacitor means.