US3568060A
Expired / Lapsed
US
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Pulse center finder employing dual counter rate with synchronous operation
Assignee: Science Accessories Corp
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Filing: 1967-10-18
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Granted: 1971-03-02
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Expires: 1987-10-18
Abstract
Abstract A device for digitally indicating the center of a pulse employing a pulse counter and a pulse generator having a fixed generating rate. Upon receipt of an initial pulse a first flipflop opens a first gating circuit and passes pulses to the counter. A second flip-flop receives the leading edge of a subsequent pulse to turn off the first gate and opens a second gate. The second gate in turn allows pulses at one-half the fixed generating rate to accumulate in the counter. The trailing edge of the second pulse changes the state of the second flip-flop and turns off the second gate. The accumulated count is now representative of the measure from the initial timing pulse to the center of the second pulse. A further flip-flop, upon receipt of a further pulse, changes state and insures that the gating circuits do not open to permit further counting. The two level counting is accomplished by a pulse frequency dividing stage connected to the pulse source, or, alternatively, by using the output of the first counter stage.
Inventors
- 👤 Joseph A Howells
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 07:42
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153; H03K5/1532; H01; H01J; H01J47/00; H01J47/10
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
223 words
An arrangement for measuring the spacing between an initial pulse and the effective time center of a subsequent pulse of variable width, comprising a pulse counter, a source of pulses having a predetermined repetition rate, frequency dividing means coupled to said source for reducing said predetermined repetition rate by half, first gating means coupling said source to said counter, second gating means coupling said frequency dividing means to said counter, a first logic circuit having first and second inputs steered to fixed values and having a third input responsive to said initial pulse for providing a first output condition, a second logic circuit having first and second inputs steered to the output and complement thereof of said first logic circuit and a third input responsive to the leading edge of said subsequent pulse for providing a second output condition and a complement thereof, said first gating means enabled by said first output condition of said first logic circuit for coupling said source to said counter, said second output condition and complement thereof coupled to respective inputs of said first and second gating means and operative to simultaneously inhibit said first gating means and enable said second gating means for coupling said frequency dividing means to said counter, and means responsive to the termination of said subsequent pulse for inhibiting said second gating means.
Claim 2
Dependent Claim
223 words
An arrangement for measuring the spacing between an initial pulse and the effective time center of a subsequent pulse of variable width, comprising a pulse counter, a source of pulses having a predetermined repetition rate, frequency dividing means coupled to said source for reducing said predetermined repetition rate by half, first gating means coupling said source to said counter, second gating means coupling said frequency dividing means to said counter, a first logic circuit having first and second inputs steered to fixed values and having a third input responsive to said initial pulse for providing a first output condition, a second logic circuit having first and second inputs steered to the output and complement thereof of said first logic circuit and a third input responsive to the leading edge of said subsequent pulse for providing a second output condition and a complement thereof, said first gating means enabled by said first output condition of said first logic circuit for coupling said source to said counter, said second output condition and complement thereof coupled to respective inputs of said first and second gating means and operative to simultaneously inhibit said first gating means and enable said second gating means for coupling said frequency dividing means to said counter, and means responsive to the termination of said subsequent pulse for inhibiting said second gating means.
Claim 3
Dependent Claim
33 words
The combination of claim 1 further including a third logic circuit connected to said second gating means and responsive to the presence of a further pulse for further inhibiting said second gating means.
Claim 4
Dependent Claim
73 words
The combination of claim 1 wherein each of said logic circuits comprises a logic flip-flop having a first input, a second input, a logic input, a reset input and a pair of complementary outputs, the first and second inputs of said first logic circuit being preset to 1 and 0 respectively, the first and second inputs of said second logic circuit each being connected to a respective output of said first logic circuit.
Claim 5
Dependent Claim
248 words
An arrangement for measuring the spacing between an initial pulse and the effective time center of a subsequent pulse of variable width, comprising a pulse counter, a source of pulses having a predetermined repetition rate, frequency dividing means coupled to said source for reducing said predetermined repetition rate by half, first gating means coupling said source to said counter, second gating means coupling said frequency dividing means to said counter, third gating means coupling said source of pulses to said frequency dividing means, means enabling said third gating means simultaneously with said second gating means, a first logic circuit having first and second inputs steered to fixed values and having a third input responsive to said initial pulse for providing a first output condition, a second logic circuit having first and second inputs steered to the output and complement thereof of said first logic circuit and a third input responsive to the leading edge of said subsequent pulse for providing a second output condition and a complement thereof, said first gating means enabled by said first output condition of said first logic circuit for coupling said source to said counter, said second output condition and complement thereof coupled to respective inputs of said first and second gating means and operative to simultaneously inhibit said first gating means and enable said second gating means for coupling said frequency dividing means to said counter, and means responsive to the termination of said subsequent pulse for inhibiting said second gating means.
Claim 6
Dependent Claim
248 words
An arrangement for measuring the spacing between an initial pulse and the effective time center of a subsequent pulse of variable width, comprising a pulse counter, a source of pulses having a predetermined repetition rate, frequency dividing means coupled to said source for reducing said predetermined repetition rate by half, first gating means coupling said source to said counter, second gating means coupling said frequency dividing means to said counter, third gating means coupling said source of pulses to said frequency dividing means, means enabling said third gating means simultaneously with said second gating means, a first logic circuit having first and second inputs steered to fixed values and having a third input responsive to said initial pulse for providing a first output condition, a second logic circuit having first and second inputs steered to the output and complement thereof of said first logic circuit and a third input responsive to the leading edge of said subsequent pulse for providing a second output condition and a complement thereof, said first gating means enabled by said first output condition of said first logic circuit for coupling said source to said counter, said second output condition and complement thereof coupled to respective inputs of said first and second gating means and operative to simultaneously inhibit said first gating means and enable said second gating means for coupling said frequency dividing means to said counter, and means responsive to the termination of said subsequent pulse for inhibiting said second gating means.
Claim 7
Dependent Claim
33 words
The combination of claim 4 further including a third logic circuit connected to said second gating means and responsive to the presence of a further pulse for further inhibiting said second gating means.
Claim 8
Dependent Claim
73 words
The combination of claim 4 wherein each of said logic circuits comprises a logic flip-flop having a first input, a second input, a logic input, a reset input and a pair of complementary outputs, the first and second inputs of said first logic circuit being preset to 1 and 0 respectively, the first and second inputs of said second logic circuit each being connected to a respective output of said first logic circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-01 | 1974-08-31 | 1975-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-01 | 1978-08-31 | 1979-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-01 | 1982-08-31 | 1983-03-02 | $7700.00 | Window Closed / Lapsed |