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Patent US3846765A successfully refreshed from Google Patents.
US3846765A
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Dynamic cell semiconductor memory with interlace refresh
Assignee: Monolithic Systems Corp
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Filing: 1973-02-14
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Granted: 1974-11-05
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Expires: 1993-02-14
Abstract
Abstract A dynamic cell memory is divided into an even address module and an odd address module, each requiring periodic refreshing of the data stored therein. A refresh interlace control is provided for automatically refreshing, on each memory cycle, a portion of the data stored in the module that is not addressed for a read or write operation. The refresh interlace control also includes timing means operable to force a refresh operation for any module if a predetermined interval of time elapses during which that module is addressed on every memory cycle for either a read or a write operation.
Inventors
- 👤 Vries R De
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:48
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
341 words
A memory system comprising: first and second memory modules each having a plurality of addressable storage locations for dynamically storing data signals as trapped charges, said charges requiring refreshing at intervals of time, means for applying addressing signals to each of said memory modules; first and second memory cycle control means for sequencing said first and second memory modules, respectively, through a read or write cycle in response to a cycle initiate signal or through a refresh cycle in response to a refresh request signal; first and second interlace control circuits for producing said refresh request signals and said cycle initiate signals; means for applying to each of said interlace control circuits an address signal indicating which memory module contains the storage locations being addressed; and, means for applying to each of sAid interlace control circuits a signal indicating whether a read or write operation is to be performed at the addressed storage location, said first interlace control circuit including, first means responsive said read and write operation signals and said address signal for producing and applying a refresh request signal to said first memory cycle control means when said address signal indicates the addressed storage location is not in said first memory module, and second means responsive to said read and write operation signals and said address signal for applying a cycle initiate signal to said first memory cycle control means when said address signal indicates the addressed storage location is in said first memory module; said second interlace control circuit including, first means responsive to said read and write operation signals and said address signal for producing and applying a refresh request signal to said second memory cycle control means when said address signal indicates the addressed storage location is not in said second memory module, and second means responsive to said read and write operation signals and said address signal for applying a cycle initiate signal to said second memory cycle control means when said address signal indicates the addressed storage location is in said second memory module.
Claim 2
Dependent Claim
341 words
A memory system comprising: first and second memory modules each having a plurality of addressable storage locations for dynamically storing data signals as trapped charges, said charges requiring refreshing at intervals of time, means for applying addressing signals to each of said memory modules; first and second memory cycle control means for sequencing said first and second memory modules, respectively, through a read or write cycle in response to a cycle initiate signal or through a refresh cycle in response to a refresh request signal; first and second interlace control circuits for producing said refresh request signals and said cycle initiate signals; means for applying to each of said interlace control circuits an address signal indicating which memory module contains the storage locations being addressed; and, means for applying to each of sAid interlace control circuits a signal indicating whether a read or write operation is to be performed at the addressed storage location, said first interlace control circuit including, first means responsive said read and write operation signals and said address signal for producing and applying a refresh request signal to said first memory cycle control means when said address signal indicates the addressed storage location is not in said first memory module, and second means responsive to said read and write operation signals and said address signal for applying a cycle initiate signal to said first memory cycle control means when said address signal indicates the addressed storage location is in said first memory module; said second interlace control circuit including, first means responsive to said read and write operation signals and said address signal for producing and applying a refresh request signal to said second memory cycle control means when said address signal indicates the addressed storage location is not in said second memory module, and second means responsive to said read and write operation signals and said address signal for applying a cycle initiate signal to said second memory cycle control means when said address signal indicates the addressed storage location is in said second memory module.
Claim 3
Dependent Claim
68 words
A memory system as claimed in claim 1 wherein means are provided for applying a read or a write signal to each of said memory cycle control means whereby the control means which has a cycle initiate signal applied thereto sequences its respective memory module through a read or a write cycle while the other memory cycle control means sequences its respective memory module through a refresh cycle.
Claim 4
Dependent Claim
18 words
A memory system as claimed in claim 2 wherein each memory module comprises an integrated circuit semiconductor memory.
Claim 5
Dependent Claim
51 words
A memory system as claimed in claim 2 wherein each of said interlace control circuits includes a third means responsive to said first means for asynchronously producing said refresh request signal if said first means does not produce a refresh request signal at least once during a fixed interval of time.
Claim 6
Dependent Claim
88 words
A memory system as claimed in claim 2 wherein each of said first means comprises a pulse generator having an output thereof connected to the input of a flipflop, and means for triggering said pulse generator in response to said read and write operation signals and said address signal to set said flipflop when said address signal indicates the addressed storage location is in the memory module associated with the interlace control circuit containing the other first means, the output from said flipflop being said refresh request signal.
Claim 7
Dependent Claim
87 words
A memory system as claimed in claim 5 wherein: each said third means comprises a retriggerable one-shot multivibrator having a timing constant shorter than an interval defined the period at which said charges must be refreshed, divided by the number of refresh cycles required to refresh all storage locations in a module, and means connecting said pulse generator to said multivibrator whereby said multivibrator is retriggered to start measuring a new timing interval each time the pulse generator causes said flipflop to produce said refresh request signal.
Claim 8
Dependent Claim
42 words
A memory system as claimed in claim 6 and further comprising: a further pulse generator responsive to said multivibrator for setting said flipflop each time the multivibrator is not retriggered during an interval of time exceeding the timing constant of the multivibrator.
Claim 9
Dependent Claim
175 words
In a dynamic memory system of the type requiring refreshing of stored data at least once during a given interval of time, the combination comprising: a plurality of memory modules each storing data at a plurality of addressable memory locations; a corresponding plurality of control means each associated with a corresponding one of said modules, for sequencing said modules through read, write, or refresh cycles; means for applying addressing signals to said memory modules to address one of said memory locations; means for applying read and write signals to all said control means; and, means for applying to all said control means an address signal indicating which memory module contains the addressed location; said control means each including first means for sequencing a read or write cycle of its associated module if said address signal indicates the addressed memory location is in that module; and, said control means each including second means for sequencing a refresh cycle of its associated module if said address signal indicates the addressed memory location is not in that module.
Claim 10
Dependent Claim
175 words
In a dynamic memory system of the type requiring refreshing of stored data at least once during a given interval of time, the combination comprising: a plurality of memory modules each storing data at a plurality of addressable memory locations; a corresponding plurality of control means each associated with a corresponding one of said modules, for sequencing said modules through read, write, or refresh cycles; means for applying addressing signals to said memory modules to address one of said memory locations; means for applying read and write signals to all said control means; and, means for applying to all said control means an address signal indicating which memory module contains the addressed location; said control means each including first means for sequencing a read or write cycle of its associated module if said address signal indicates the addressed memory location is in that module; and, said control means each including second means for sequencing a refresh cycle of its associated module if said address signal indicates the addressed memory location is not in that module.
Claim 11
Dependent Claim
106 words
The combination as claimed in claim 8 wherein said addressable storage locations are logically arranged in a matrix of rows and columns in each of said modules, said control means each including a refresh address counter for addressing said storage locations a row at a time, one row during each refresh cycle of the memory module, and said control means includes further means for initiating a refresh cycle of the associated memory module if said second means does not initiate a refresh cycle at least as often as said given interval of time divided by the number of rows of storage locations in the memory module.
Claim 12
Dependent Claim
45 words
The combination as claimed in claim 9 wherein said refresh address counter is a modulo N counter, N being the number of rows of storage locations in a memory module, said control means including means for incrementing said counter by one on each refresh cycle.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-04 | 1978-05-06 | 1978-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-04 | 1982-05-06 | 1982-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-04 | 1986-05-06 | 1986-11-05 | $7700.00 | Window Closed / Lapsed |