Operand comparator

Claim 2

In a data processing system an operand comparator for comparing first and second operands comprising, first means for simultaneously comparing corresponding bits in the first and second operands to detect the first occurrence, from highest-order toward lowest-order, of a first equality relationship between corresponding bits, second means for simultaneously comparing corresponding bits in the first and second operands to detect the first occurrence, from highest-order toward Lowest-order, of a second equality relationship between corresponding bits, and third means for selecting said first or second means whereby said first or second equality relationship is selected.

Claim 3

The comparator of claim 1 wherein, for operands in fixed point arithmetic, said first equality relationship is identity of bits when one of said operands is positive in binary notation and the other of said operands is negative in 2''s complement notation and wherein said second equality relationship is non-identity of bits when both operands are positive in binary notation or both operands are negative in 2''s complement notation.

Claim 4

The comparator of claim 1 wherein, for operands in normalized floating point arithmetic, said second equality relationship is non-identity of corresponding bits excluding the sign bits, and said third means selects said second means.

Claim 7

In a data processing system operative for executing instructions and employing first and second operands in connection with the execution of instructions, said first and second operands including a plurality of ordered bits arrayed from highest-order to lowest-order, an operand comparator for comparing the first and second operands within the data processing system, said comparator formed by a plurality of electronic circuits for operating upon said operands on a bit-by-bit basis, said operand comparator comprising, first means including a plurality of levels of logic for simultaneously comparing corresponding bits in the first and second operands to detect the first occurrence, from highest-order toward lowest-order, of an identity relationship between corresponding bits in said first and second operands, second means including a plurality of levels of logic for simultaneously comparing corresponding bits in the first and second operands to detect the first occurrence, from highest-order toward lowest-order, of a non-identity relationship between corresponding bits in said first and second operands, and third means for selecting said first or second means to select said identity or non-identity relationship.

Claim 8

In a data processing system operative for executing instructions and employing first and second operands in connection with the execution of instructions, said first and second operands including a plurality of ordered bits arrayed from highest-order to lowest-order, an operand comparator for comparing the first and second operands within the data processing system, said comparator formed by a plurality of electronic circuits for operating upon said operands on a bit-by-bit basis, said operand comparator comprising, first means including a plurality of levels of logic for simultaneously comparing corresponding bits in the first and second operands to detect the first occurrence, from highest-order toward lowest-order, of an identity relationship between corresponding bits in said first and second operands, second means including a plurality of levels of logic for simultaneously comparing corresponding bits in the first and second operands to detect the first occurrence, from highest-order toward lowest-order, of a non-identity relationship between corresponding bits in said first and second operands, and third means for selecting said first or second means to select said identity or non-identity relationship.

Claim 9

The comparator of claim 5 wherein for operands in fixed point arithmetic, said third means includes means for selecting said first means when one of said operands is positive in binary notation and the other of said operands is negative in 2''s complement notation and wherein said third means includes means for selecting said second means when both operands are positive in binary notation or both operands are negative in 2''s complement notation.

Claim 10

The comparator of claim 5 wherein, for operands in normalized floating point arithmetic, said third means includes means for selecting said second means where said equality relationship is non-identity of corresponding bits excluding the sign bits.

Claim 11

In a data processing system operative for executing instructions, said system including apparatus for fetching and storing first and second operands in connection with the execution of instructions, said first and second operands including a plurality of ordered bits defined by the signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, where n equals the number of bits, a comparator formed by a plurality of electronic circuits comprising, a first logic level defining said operands as bipolar signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, a second logic level including means for forming the EXCLUSIVE-OR of said operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -DIF and including means for forming the EXCLUSIVE-NOR of the operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -SAM, a third logic level including means for combining groups of said signals -DIF and including means for combining groups of said signals -SAM, a fourth logic level including means for combining the signals from said first, second and third logic levels to form signals FIRST DIF which specify that the first difference from high-order to low-order between corresponding bits in said first and said second operands is a 1 in said first operand, and said fourth logic level further including means for combining the signals from said first, second and third logic levels to form signals FIRST SAM which specify that the first identity between the bits in said first and second operands is a 1.

Claim 12

In a data processing system operative for executing instructions, said system including apparatus for fetching and storing first and second operands in connection with the execution of instructions, said first and second operands including a plurality of ordered bits defined by the signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, where n equals the number of bits, a comparator formed by a plurality of electronic circuits comprising, a first logic level defining said operands as bipolar signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, a second logic level including means for forming the EXCLUSIVE-OR of said operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -DIF and including means for forming the EXCLUSIVE-NOR of the operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -SAM, a third logic level including means for combining groups of said signals -DIF and including means for combining groups of said signals -SAM, a fourth logic level including means for combining the signals from said first, second and third logic levels to form signals FIRST DIF which specify that the first difference from high-order to low-order between corresponding bits in said first and said second operands is a 1 in said first operand, and said fourth logic level further including means for combining the signals from said first, second and third logic levels to form signals FIRST SAM which specify that the first identity between the bits in said first and second operands is a 1.

Claim 13

The operand comparaor of claim 8 further comprising means for sensing the high-order bits of said first and second operands for detecting identity and providing a signal OPS POS when said high-order bits re both 0''s and for providing a signal OPS NEG when said high-order bits are both 1''s, means responsive to said SAM signals for indicating that the absolute value of said first operand equals the absolute value of said second operand providing a signal OP1 OP2 S, means responsive to said OPS POS, said SAM and said FIRST DIF signals for specifying that the absolute value of said first operand is greater than or less than the absolute value of said second operand.

Claim 14

The operand comparator of claim 8 wherein said DIF signals include the signals DIF(0) for indicating that said first and second operands are of opposite signs, said comparator further including means responsive to said FIRST SAM signals and said DIF(0) signals for indicating the greater than and less than equality relationships between said first and said second operands.

Claim 15

The operand comparator of claim 10 further including means responsive to said FIRST SAM signals for detecting when all lower-order bits after the first identity bit which is a 1 are all 0''s thereby specifying that the absolute value of said first operand is equal to the absolute value of said second operand.

Claim 16

In a data processing system operative for executing instructions, said system including apparatus for fetching and storing first and second operands in connection with the execution of instructions, said first and second operands including a plurality of ordered bits defined by the signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, where n equals the number of bits, a comparator formed by a plurality of electronic circuits comprising, a first logic level defining said operands as bipolar signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, a second logic level including means for forming the EXCLUSIVE-OR of said operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -DIF and including means for forming the EXCLUSIVE-NOR of the operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -SAM, a third logic level including means for combining groups of said signals -DIF and including means for combining groups of said signals -SAM, a fourth logic level including means for combining the signals from said first, second and third logic levels to form signals FIRST DIF which specify that the first difference from high-order to low-order between corresponding bits in said first and said seconD operands is a 1 in said first operand, and said fourth logic level further including means for combining the signals from said first, second and third logic levels to form signals FIRST SAM which specify that the first identity between the bits in said first and second operands is a 1, means responsive to said FIRST SAM signals when both said operands are positive and when said first identity is a 1 for indicating that an overflow will exist in the addition of said first and second operands, means responsive to the absence of identity in any corresponding bit position of said first and second operands when both said operands are negative to indicate that an overflow will exist in the addition of said first and second operands, means responsive to said FIRST SAM signals when both said operands are negative and when said first identity is a 0 for indicating that an overflow will exist in the addition of said first and second operands.

Claim 17

In a data processing system operative for executing instructions, said system including apparatus for fetching and storing first and second operands in connection with the execution of instructions, said first and second operands including a plurality of ordered bits defined by the signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, where n equals the number of bits, a comparator formed by a plurality of electronic circuits comprising, a first logic level defining said operands as bipolar signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, a second logic level including means for forming the EXCLUSIVE-OR of said operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -DIF and including means for forming the EXCLUSIVE-NOR of the operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -SAM, a third logic level including means for combining groups of said signals -DIF and including means for combining groups of said signals -SAM, a fourth logic level including means for combining the signals from said first, second and third logic levels to form signals FIRST DIF which specify that the first difference from high-order to low-order between corresponding bits in said first and said seconD operands is a 1 in said first operand, and said fourth logic level further including means for combining the signals from said first, second and third logic levels to form signals FIRST SAM which specify that the first identity between the bits in said first and second operands is a 1, means responsive to said FIRST SAM signals when both said operands are positive and when said first identity is a 1 for indicating that an overflow will exist in the addition of said first and second operands, means responsive to the absence of identity in any corresponding bit position of said first and second operands when both said operands are negative to indicate that an overflow will exist in the addition of said first and second operands, means responsive to said FIRST SAM signals when both said operands are negative and when said first identity is a 0 for indicating that an overflow will exist in the addition of said first and second operands.

Claim 18

In a data processing system operative for executing instructions, said system including apparatus for fetching and storing first and second operands in connection with the execution of instructions, said first and second operands including a plurality of ordered bits defined by the signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, where n equals the number of bits, a comparator formed by a plurality of electronic circuits comprising, a first logic level defining said operands as bipolar signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, a second logic level including means for forming the EXCLUSIVE-OR of said operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -DIF and including means for forming the EXCLUSIVE-NOR of the operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -SAM, a third logic level including means for combining groups of said signals -DIF and including means for combining groups of said signals -SAM, a fourth logic level icluding means for combining the signals from said first, second and third logic levels to form signals FIRST DIF which specify that the first difference from high-order to low-order between corresponding bits in said first and said second operands is a 1 in said first operand, and said fourth logic level further including means for combining the signals from said first, second and third logic levels to form signals FIRST SAM which specify that the first identity between the bits in said first and second operands is a 1, means responsive to said FIRST DIF signals indicating an absence of any difference when said operands are of opposite signs to indicate an overflow will exist in a subtraction of said operands, means responsive to said FIRST DIF signals when said first operand is positive and includes a 1 in the first corresponding non-identity location when said second operand is negative and includes a 0 to indicate an overflow will exist in a subtraction of said operands, means responsive to said FIRST DIF signals when said first operand is negative and includes a 0 in the first non-identity position while the second operand is positive and includes a 1 in the corresponding bit position to indicate an overflow will exist in the subtraction of said operands.

Claim 19

In a data processing system operative for executing instructions, said system including apparatus for fetching and storing first and second operands in connection with the execution of instructions, said first and second operands including a plurality of ordered bits defined by the signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, where n equals the number of bits, a comparator formed by a plurality of electronic circuits comprising, a first logic level defining said operands as bipolar signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, a second logic level including means for forming the EXCLUSIVE-OR of said operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -DIF and including means for forming the EXCLUSIVE-NOR of the operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -SAM, a third logic level including means for combining groups of said signals -DIF and including means for combining groups of said signals -SAM, a fourth logic level icluding means for combining the signals from said first, second and third logic levels to form signals FIRST DIF which specify that the first difference from high-order to low-order between corresponding bits in said first and said second operands is a 1 in said first operand, and said fourth logic level further including means for combining the signals from said first, second and third logic levels to form signals FIRST SAM which specify that the first identity between the bits in said first and second operands is a 1, means responsive to said FIRST DIF signals indicating an absence of any difference when said operands are of opposite signs to indicate an overflow will exist in a subtraction of said operands, means responsive to said FIRST DIF signals when said first operand is positive and includes a 1 in the first corresponding non-identity location when said second operand is negative and includes a 0 to indicate an overflow will exist in a subtraction of said operands, means responsive to said FIRST DIF signals when said first operand is negative and includes a 0 in the first non-identity position while the second operand is positive and includes a 1 in the corresponding bit position to indicate an overflow will exist in the subtraction of said operands.

Claim 20

In a data processing system operative for executing instructions including comparison, addition and subtraction instructions, said system including apparatus for fetching and storing first and second operands in connection with the execution of instructions, said first and second operands including a plurality of ordered bits defined by the signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, where n equals the number of bits, a method of electronic cOmparison comprising the steps of, forming bipolar signals + or - a(0 . . . n) and + or - b(0 . . . n) for defining said first and second operands, respectively, forming the EXCLUSIVE-OR of said first and second operands on a bit-by-bit basis to form the signals -DIF, forming the EXCLUSIVE-NOR of the first and second operands on a bit-by-bit basis to form the signals -SAM, logically combining groups of said signals -DIF, logically combining groups of said signals -SAM to form the signals -DIF(G) and -SAM(G), respectively, means for combining said signals + or - a(0 . . . n), + or -b(0 . . . n), -DIF, -SAM, -DIF(G) and -SAM(G) forming the signals FIRST DIF which specify that the first difference from high-order to low-order between corresponding bits in said first and said second operands is a 1 and forming the signals FIRST SAM which specify that the first identity between the bits in said first and second operands is a 1.

Claim 21

In a data processing system operative for executing instructions including comparison, addition and subtraction instructions, said system including apparatus for fetching and storing first and second operands in connection with the execution of instructions, said first and second operands including a plurality of ordered bits defined by the signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, where n equals the number of bits, a method of electronic cOmparison comprising the steps of, forming bipolar signals + or - a(0 . . . n) and + or - b(0 . . . n) for defining said first and second operands, respectively, forming the EXCLUSIVE-OR of said first and second operands on a bit-by-bit basis to form the signals -DIF, forming the EXCLUSIVE-NOR of the first and second operands on a bit-by-bit basis to form the signals -SAM, logically combining groups of said signals -DIF, logically combining groups of said signals -SAM to form the signals -DIF(G) and -SAM(G), respectively, means for combining said signals + or - a(0 . . . n), + or -b(0 . . . n), -DIF, -SAM, -DIF(G) and -SAM(G) forming the signals FIRST DIF which specify that the first difference from high-order to low-order between corresponding bits in said first and said second operands is a 1 and forming the signals FIRST SAM which specify that the first identity between the bits in said first and second operands is a 1.

Claim 22

In a data processing system, an operand comparator for comparing first and second operands comprising, first means for simultaneously comparing corresponding bits in the first and second operands to detect the first occurrence from highest-order toward lowest-order, of a pre-determined equality relationship between corresponding bits, second means for specifying a type of operation being performed on said first and second operands, third means for combining signals from said first and second means for determining an equality relationship between said first and second operands.

Claim 23

In a data processing system, an operand comparator for comparing first and second operands comprising, first means for simultaneously comparing corresponding bits in the first and second operands to detect the first occurrence from highest-order toward lowest-order, of a pre-determined equality relationship between corresponding bits, second means for specifying a type of operation being performed on said first and second operands, third means for combining signals from said first and second means for determining an equality relationship between said first and second operands.

Claim 24

In a data processing system operative for executing instructions, said system including apparatus for fetching and storing first and second operands in connection with the execution of instructions, said first and second operands including a plurality of ordered bits defined by the signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, where n equals the number of bits, a comparator formed by a plurality of electronic circuits comprising, a first logic level defining said operands as bipolar signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, a second logic level including means for forming the EXCLUSIVE-OR of said operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -DIF and including means for forming the EXCLUSIVE-NOR of the operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -SAM, a third logic level including means for combining groups of said signals -DIF and including means for combining groups of said signals -SAM, a fourth logic level including means for combining the signals from said first, second and third logic levels to form signals FIRST DIF which specify that the first difference from high-order to low-order between corresponding bits in said first and said second operands is a 1 in said first operand, and said fourth logic level further including means for combining the signals from said first, second and third logic levels to form signals FIRST SAM which specify that the first identity between the bits in said first and second operands is a 1, a plurality of circuits responsive to the signals of said first, second, third and fourth logic levels for specifying a plurality of equality relationships between said first and second operands.

Claim 25

In a data processing system operative for executing instructions, said system including apparatus for fetching and storing first and second operands in connection with the execution of instructions, said first and second operands including a plurality of ordered bits defined by the signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, where n equals the number of bits, a comparator formed by a plurality of electronic circuits comprising, a first logic level defining said operands as bipolar signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, a second logic level including means for forming the EXCLUSIVE-OR of said operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -DIF and including means for forming the EXCLUSIVE-NOR of the operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -SAM, a third logic level including means for combining groups of said signals -DIF and including means for combining groups of said signals -SAM, a fourth logic level including means for combining the signals from said first, second and third logic levels to form signals FIRST DIF which specify that the first difference from high-order to low-order between corresponding bits in said first and said second operands is a 1 in said first operand, and said fourth logic level further including means for combining the signals from said first, second and third logic levels to form signals FIRST SAM which specify that the first identity between the bits in said first and second operands is a 1, a plurality of circuits responsive to the signals of said first, second, third and fourth logic levels for specifying a plurality of equality relationships between said first and second operands.

Claim 26

In a data processing system operative for executing instructions, said system including apparatus for fetching and storing first and second operands in connection with the execution of instructions, said first and second operands including a plurality of ordered bits defined by the signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, where n equals the nUmber of bits, a comparator formed by a plurality of electronic circuits comprising, a first logic level defining said operands as bipolar signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, a second logic level including means for forming the EXCLUSIVE-OR of said operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -DIF and including means for forming the EXCLUSIVE-NOR of the operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -SAM, a third logic level including means for combining groups of said signals -DIF and including means for combining groups of said signals -SAM, a fourth logic level including means for combining the signals from said first, second and third logic levels to form signals FIRST DIF which specify that the first difference from high-order to low-order between corresponding bits in said first and said second operands is a 1 in said first operand, and said fourth logic level further including means for combining the signals from said first, second and third logic levels to form signals FIRST SAM which specify that the first identity between the bits in said first and second operands is a 1, a plurality of circuits responsive to the signals of said first, second, third and fourth logic levels for specifying a plurality of equality relationships between said first and second operands, means responsive to the instruction processing apparatus and to said plurality of circuits for setting a condition code.

Claim 27

In a data processing system operative for executing instructions, said system including apparatus for fetching and storing first and second operands in connection with the execution of instructions, said first and second operands including a plurality of ordered bits defined by the signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, where n equals the nUmber of bits, a comparator formed by a plurality of electronic circuits comprising, a first logic level defining said operands as bipolar signals + or - a(0 . . . n) and + or - b(0 . . . n), respectively, a second logic level including means for forming the EXCLUSIVE-OR of said operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -DIF and including means for forming the EXCLUSIVE-NOR of the operands + or - a(0 . . . n) and + or - b(0 . . . n) on a bit-by-bit basis to form signals -SAM, a third logic level including means for combining groups of said signals -DIF and including means for combining groups of said signals -SAM, a fourth logic level including means for combining the signals from said first, second and third logic levels to form signals FIRST DIF which specify that the first difference from high-order to low-order between corresponding bits in said first and said second operands is a 1 in said first operand, and said fourth logic level further including means for combining the signals from said first, second and third logic levels to form signals FIRST SAM which specify that the first identity between the bits in said first and second operands is a 1, a plurality of circuits responsive to the signals of said first, second, third and fourth logic levels for specifying a plurality of equality relationships between said first and second operands, means responsive to the instruction processing apparatus and to said plurality of circuits for setting a condition code.