Digital comparator utilizing dual circuits for self-checking

Claim 1

A digital comparator for assessing whether a measured binary response from a test object lies within predetermined tolerance limits, comprising: two banks of identical comparator bit units, each unit including an upper register for storing one bit of the upper tolerance limit, a lower register for storing one bit of the lower tolerance limit, a measured value register for storing one bit of the measured binary response, and comparison gating means having inputs responsive to the bits in each of the said registers, each unit having first, second and third outputs for signals indicating whether the measured bit is higher than, within, or lower than the tolerance limits respectively; each unit further including input gating means operable in a first state to cause said comparison gating means to compare the measured response bit with the upper register bit and operable in a second state to cause the comparison gating means to compare the measured response bit with the lower register bit; the comparator further including means responsive to said first output for switching the input gating means from the first state to the second state, the said second output from each unit being connected through further gating means to the input of the next unit in both of the said banks whereby the comparison of the successive bits is halted unless the respective output signals from the corresponding units in the two banks are identical.