US3825771A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Igfet inverter circuit
Assignee: AT&T Inc
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Filing: 1972-12-04
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Granted: 1974-07-23
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Expires: 1992-12-04
Abstract
Abstract A semiconductor inverter circuit consists of a driver, a load, and two other IGFETs. One of the two IGFETs is wired as a diode that is connected to the gate of the load IGFET. The drain of the other IGFET is also connected to the gate of the load IGFET. The source and drain of the load and diver are connected together and serve as the output terminal of the circuit. The gate of the diver serves as the input terminal. The IGFET connected as a diode serves to hold the load on while the output signal drops from a high to a low state. This significantly decreases the time necessary to achieve this change of state as compared to the case in which the load turns off. The fourth IGFET serves to turn off the load when the output signal is to assume the high state.
Inventors
- 👤 Harry J Boll
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:37
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01728
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
179 words
An inverter circuit comprising: first, second, third, and fourth field effect transistors; the drain of the first transistor being coupled to the source of the second transistor; a first terminal being coupled to the gate of the first transistor and a second terminal being coupled to the drain of the first transistor; the gate of the second transistor being coupled to the source of the third transistor and the drain of the fourth transistor; the drain of the second transistor being coupled to the gate of the fourth transistor; a third terminal being coupled to the drain of the second transistor; the gate and drain of the third transistor being coupled together; a fourth terminal being coupled to the drain of the third transistor; a fifth terminal being coupled to the source of the first transistor; the second transistor being characterized by a first capacitance coupling the circuit path between the drain and gate and a second capacitance coupling the circuit path between the gate and source; and a third capacitance coupled to the gate of the second transistor.
Claim 2
Dependent Claim
179 words
An inverter circuit comprising: first, second, third, and fourth field effect transistors; the drain of the first transistor being coupled to the source of the second transistor; a first terminal being coupled to the gate of the first transistor and a second terminal being coupled to the drain of the first transistor; the gate of the second transistor being coupled to the source of the third transistor and the drain of the fourth transistor; the drain of the second transistor being coupled to the gate of the fourth transistor; a third terminal being coupled to the drain of the second transistor; the gate and drain of the third transistor being coupled together; a fourth terminal being coupled to the drain of the third transistor; a fifth terminal being coupled to the source of the first transistor; the second transistor being characterized by a first capacitance coupling the circuit path between the drain and gate and a second capacitance coupling the circuit path between the gate and source; and a third capacitance coupled to the gate of the second transistor.
Claim 3
Dependent Claim
21 words
The apparatus of claim 1 wherein the source of the fourth transistor is coupled to the drain of the first transistor.
Claim 4
Dependent Claim
18 words
The apparatus of claim 2 wherein the four field effect transistors are p-channel insulated gate field effect transistors.
Claim 5
Dependent Claim
28 words
The apparatus of claim 3 further comprising a first voltage pulse circuit coupled to the third terminal and a second voltage pulse circuit coupled to the fourth terminal.
Claim 6
Dependent Claim
41 words
The apparatus of claim 1 further comprising a fifth transistor, the gate of the fifth transistor being coupled to the gate of the first transistor and the drain of the fifth transistor being coupled to the source of the fourth transistor.
Claim 7
Dependent Claim
17 words
The apparatus of claim 5 wherein the five transistors are all p-channel insulated gate field effect transistors.
Claim 8
Dependent Claim
17 words
The apparatus of claim 5 further comprising a first voltage pulse circuit coupled to the third terminal.
Claim 9
Dependent Claim
129 words
A semiconductor inverter circuit comprising: first, second, third, and fourth field effect transistors, the drain of the first transistor being coupled to the source of the second transistor; the gate of the second transistor being coupled to the source of the third transistor and the drain of the fourth transistor; the gate and drain of the third transistor being coupled together; the source of the fourth transistor being coupled to the drain of the first transistor; a first capacitance coupling together the drain and gate of the second transistor; a second capacitance coupling together the source and gate of the second transistor; a third capacitance coupled to the gate of the second transistor; and the gate of the fourth transistor being coupled to the drain of the second transistor.
Claim 10
Dependent Claim
129 words
A semiconductor inverter circuit comprising: first, second, third, and fourth field effect transistors, the drain of the first transistor being coupled to the source of the second transistor; the gate of the second transistor being coupled to the source of the third transistor and the drain of the fourth transistor; the gate and drain of the third transistor being coupled together; the source of the fourth transistor being coupled to the drain of the first transistor; a first capacitance coupling together the drain and gate of the second transistor; a second capacitance coupling together the source and gate of the second transistor; a third capacitance coupled to the gate of the second transistor; and the gate of the fourth transistor being coupled to the drain of the second transistor.
Claim 11
Dependent Claim
145 words
A semiconductor inverter circuit comprising: first, second, third, fourth, and fifth field effect transistors; the drain of the first transistor being coupled to the source of the second transistor; the gate of the second transistor being coupled to the source of the third transistor and the drain of the fourth transistor; the gate and drain of the third transistor being coupled together; the source of the fourth transistor being coupled to the drain of the fifth transistor; the gate of the fifth transistor being coupled to the gate of the first transistor; the circuit path between the drain and gate of the second transistor being characterized by a first capacitance; and the circuit path between the source and gate of the second transistor being characterized by a second capacitance; and the gate of the fourth transistor being coupled to the drain of the second transistor.
Claim 12
Dependent Claim
145 words
A semiconductor inverter circuit comprising: first, second, third, fourth, and fifth field effect transistors; the drain of the first transistor being coupled to the source of the second transistor; the gate of the second transistor being coupled to the source of the third transistor and the drain of the fourth transistor; the gate and drain of the third transistor being coupled together; the source of the fourth transistor being coupled to the drain of the fifth transistor; the gate of the fifth transistor being coupled to the gate of the first transistor; the circuit path between the drain and gate of the second transistor being characterized by a first capacitance; and the circuit path between the source and gate of the second transistor being characterized by a second capacitance; and the gate of the fourth transistor being coupled to the drain of the second transistor.
Claim 13
Dependent Claim
129 words
An inverter circuit comprising: first and second field effect transistors, the drain of the first transistor being coupled to the source of the second transistor; voltage bias circuit means comprising first and second terminals; a third field effect transistor, the gate of the second transistor being coupled to the drain of the third transistor and to the first terminal of the voltage bias means; the circuit path between the drain and the gate of the second transistor being defined by a first capacitance; the circuit path between the source and gate of the second transistor being defined by a second capacitance; a third capacitance being coupled to the gate of the second transistor; and the gate of the third transistor being coupled to the drain of the second transistor.
Claim 14
Dependent Claim
129 words
An inverter circuit comprising: first and second field effect transistors, the drain of the first transistor being coupled to the source of the second transistor; voltage bias circuit means comprising first and second terminals; a third field effect transistor, the gate of the second transistor being coupled to the drain of the third transistor and to the first terminal of the voltage bias means; the circuit path between the drain and the gate of the second transistor being defined by a first capacitance; the circuit path between the source and gate of the second transistor being defined by a second capacitance; a third capacitance being coupled to the gate of the second transistor; and the gate of the third transistor being coupled to the drain of the second transistor.
Claim 15
Dependent Claim
150 words
A logic circuit comprising: first switching means comprising first and second terminals and a control terminal for selectively establishing an essentially short circuit or open circuit condition between the first and second terminals thereof; a field effect transistor having source, drain, and gate terminals, the source terminal being coupled to the second terminal of the first switching means; first capacitive circuit means coupling together the drain and gate terminals of the transistor and second capacitive circuit means coupling together the source and gate terminals of the transistor; voltage biasing means coupled to the gate terminal of the transistor; and second switching means comprising first and second terminals and a control terminal for selectively establishing an essentially short or open circuit condition between the first and second terminals thereof, the gate and the drain of the transistor being coupled to the second and control terminal of the second switching means, respectively.
Claim 16
Dependent Claim
150 words
A logic circuit comprising: first switching means comprising first and second terminals and a control terminal for selectively establishing an essentially short circuit or open circuit condition between the first and second terminals thereof; a field effect transistor having source, drain, and gate terminals, the source terminal being coupled to the second terminal of the first switching means; first capacitive circuit means coupling together the drain and gate terminals of the transistor and second capacitive circuit means coupling together the source and gate terminals of the transistor; voltage biasing means coupled to the gate terminal of the transistor; and second switching means comprising first and second terminals and a control terminal for selectively establishing an essentially short or open circuit condition between the first and second terminals thereof, the gate and the drain of the transistor being coupled to the second and control terminal of the second switching means, respectively.
Claim 17
Dependent Claim
22 words
The apparatus of claim 11 wherein the first terminal of the second switching means is coupled to the source of the transistor.
Claim 18
Dependent Claim
77 words
The apparatus of claim 11 further comprising: a third switching means comprising a control terminal and first and second terminals for selectively establishing an essential short circuit and an open circuit condition between the first and second terminals thereof, the control terminal of the third switching means being coupled to the control terminal of the first switching means, the second terminal of the third switching means being coupled to the fiRst terminal of the second switching means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-07-22 | 1978-01-21 | 1978-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-07-22 | 1982-01-21 | 1982-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-07-22 | 1986-01-21 | 1986-07-23 | $7700.00 | Window Closed / Lapsed |