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US3755689A
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US
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Two-phase three-clock mos logic circuits
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1971-12-30
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Granted: 1973-08-28
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Expires: 1991-12-30
Abstract
Abstract Ratioless MOS logic circuits are disclosed which use two nonoverlapping clocks for two-phase control of signal propagation and a third precharge clock, of shorter duration, at double the repetition rate of the first two clocks for precharging storage node capacitance. In each circuit, an electrical network is provided having a transistor connected as a precharge diode for applying the precharge clock to the storage node capacitance through a clocked transfer gate transistor. A logic network is provided having a net of transistors connected, in parallel with the precharge diode transistor, as a relay logic network to selectively discharge the storage node capacitor, after the precharge clock. Where required, a novel dynamic buffer is provided having an output which is essentially insensitive to crossover capacitance effects.
Inventors
- 👤 B Elmer
- 👤 M Eklund
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:38
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
143 words
Ratioless logic circuits comprising: A. a first phase logic including 1. a first precharge, diode connected, transistor, 2. a storage capacitor, 3. a first transfer gate transistor connected in series between said first precharge diode and said first storage capacitor, 4. a first logic network, connected in parallel with said first precharge diode, for selectively discharging said storage capacitor; B. a second phase logic circuit including 1. a second precharge, diode connected, transistor, 2. a storage capacitor, 3. a second transfer gate transistor connected in series between said second precharge diode and said second storage capacitor, 4. a second logic network, connected in parallel with said second precharge diode, for selectively discharging said storage capacitor; C. a common precharge bus connected to said first precharge diode and said second precharge diode; D. means connecting said first storage capacitor to said second logic network.
Claim 2
Dependent Claim
143 words
Ratioless logic circuits comprising: A. a first phase logic including 1. a first precharge, diode connected, transistor, 2. a storage capacitor, 3. a first transfer gate transistor connected in series between said first precharge diode and said first storage capacitor, 4. a first logic network, connected in parallel with said first precharge diode, for selectively discharging said storage capacitor; B. a second phase logic circuit including 1. a second precharge, diode connected, transistor, 2. a storage capacitor, 3. a second transfer gate transistor connected in series between said second precharge diode and said second storage capacitor, 4. a second logic network, connected in parallel with said second precharge diode, for selectively discharging said storage capacitor; C. a common precharge bus connected to said first precharge diode and said second precharge diode; D. means connecting said first storage capacitor to said second logic network.
Claim 3
Dependent Claim
102 words
The logic circuit of claim 1 further comprising: E. a pair of push-pull transistors, series connected from the gate of said first transfer gate transistor of said first phase logic circuit to ground, for providing a buffered output signal; F. said second storage capacitor being connected to the first one of said push-pull transistors, for selectively turning it on; G. a buffer capacitor, connected to the gate of the second one of said push-pull transistors, for selectively turning it on; H. a control transistor, connected for charging and selectively discharging said buffer capacitor, and having its gate connected to said second capacitor.
Claim 4
Dependent Claim
3 words
a storage capacitor,
Claim 5
Dependent Claim
3 words
a storage capacitor,
Claim 6
Dependent Claim
3 words
a storage capacitor,
Claim 7
Dependent Claim
3 words
a storage capacitor,
Claim 8
Dependent Claim
18 words
a first transfer gate transistor connected in series between said first precharge diode and said first storage capacitor,
Claim 9
Dependent Claim
18 words
a first transfer gate transistor connected in series between said first precharge diode and said first storage capacitor,
Claim 10
Dependent Claim
125 words
A dynamic buffer for a ratioless logic circuit in a system having two phase clock buses comprising: A. a storage capacitor for storing information bits; B. a pair of push-pull transistors, series connected from one of the clock buses to ground, for providing a buffered output signal; C. said storage capacitor being connected to a first one of said push-pull transistors, for selectively turning it on; D. a buffer capacitor, connected to the gate of the second one of said push-pull transistors, for selectively turning it on; E. a control transistor, connected for charging and selectively discharging said buffer capacitor, and having its gate connected to said storage capacitor in such a manner that said buffer capacitor is discharged when said storage capacitor is charged.
Claim 11
Dependent Claim
125 words
A dynamic buffer for a ratioless logic circuit in a system having two phase clock buses comprising: A. a storage capacitor for storing information bits; B. a pair of push-pull transistors, series connected from one of the clock buses to ground, for providing a buffered output signal; C. said storage capacitor being connected to a first one of said push-pull transistors, for selectively turning it on; D. a buffer capacitor, connected to the gate of the second one of said push-pull transistors, for selectively turning it on; E. a control transistor, connected for charging and selectively discharging said buffer capacitor, and having its gate connected to said storage capacitor in such a manner that said buffer capacitor is discharged when said storage capacitor is charged.
Claim 12
Dependent Claim
18 words
a second transfer gate transistor connected in series between said second precharge diode and said second storage capacitor,
Claim 13
Dependent Claim
18 words
a second transfer gate transistor connected in series between said second precharge diode and said second storage capacitor,
Claim 14
Dependent Claim
46 words
a second logic network, connected in parallel with said second precharge diode, for selectively discharging said storage capacitor; C. a common precharge bus connected to said first precharge diode and said second precharge diode; D. means connecting said first storage capacitor to said second logic network.
Claim 15
Dependent Claim
46 words
a second logic network, connected in parallel with said second precharge diode, for selectively discharging said storage capacitor; C. a common precharge bus connected to said first precharge diode and said second precharge diode; D. means connecting said first storage capacitor to said second logic network.
Claim 16
Dependent Claim
25 words
a first logic network, connected in parallel with said first precharge diode, for selectively discharging said storage capacitor; B. a second phase logic circuit including
Claim 17
Dependent Claim
25 words
a first logic network, connected in parallel with said first precharge diode, for selectively discharging said storage capacitor; B. a second phase logic circuit including
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-27 | 1977-02-26 | 1977-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-27 | 1981-02-26 | 1981-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-27 | 1985-02-26 | 1985-08-28 | $7700.00 | Window Closed / Lapsed |