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US3815100A Expired / Lapsed US ⏱️ 0.0 years remaining

Self-clocking system utilizing guaranteed bit transition

Assignee: Searle Medidata Inc
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Filing: 1972-11-07
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Granted: 1974-06-04
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Expires: 1992-11-07
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Abstract

Abstract A system for digitizing signals for recording and/or transmission in a self-clocking mode. Simplified electronics are provided to sample an analog signal, typically an electrocardiogram signal, and convert its amplitude to a digital representation which is subsequently transformed into a simply generated, guaranteed bit transition self-clocking binary signal for use in medical data recording and transmission.

Inventors

  • 👤 J Winchester
  • 👤 E Rawson

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 02:11
CPC Classifications
A; A61; A61B; A61B5/00; A61B5/0002; A61B5/0004; A61B5/0006; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1407; G11B20/1419; H; H03; H03M; H03M1/00; H03M1/12; H03M1/50

Claims Analysis

Total Claims: 17
Claim 1
Independent Claim 105 words
A system for providing digital signals to a channel in a self-clocking format, said system comprising: means for receiving data words to be applied to said data channel; said data words comprising a sequence of digital bits of plural levels; means for generating a signal having transitions between maximum and minimum signal levels in response to each of said bits in received data words; means responsive to a predetermined bit level in said recieved data words for producing an additional transition in said generated signal coincident with said predetermined bit level; and means for applying said generated signal with said additional transitions to said channel.
Claim 2
Independent Claim 105 words
A system for providing digital signals to a channel in a self-clocking format, said system comprising: means for receiving data words to be applied to said data channel; said data words comprising a sequence of digital bits of plural levels; means for generating a signal having transitions between maximum and minimum signal levels in response to each of said bits in received data words; means responsive to a predetermined bit level in said recieved data words for producing an additional transition in said generated signal coincident with said predetermined bit level; and means for applying said generated signal with said additional transitions to said channel.
Claim 3
Dependent Claim 30 words
The system for providing digital signals to a channel of claim 1 further including: means for extending the time between transitions in said generated signal after said received data words.
Claim 4
Dependent Claim 162 words
The system of claim 1 further including: means for recovering the signal applied to said channel; means responsive to the interval between transitions in said recovered signal for providing a first output signal when said interval exceeds a predetermined portion of the period between bits in received data words, said predetermined portion being intermediate 50 percent and 100 percent of said period; means operative in response to the interval between transitions in said recovered signal for providing a second output signal whenever said interval is less than a further predetermined portion of the period between bits in received data words, said further predetermined portions being intermediate 50 percent and 100 percent of said period; and means for providing a digital output signal with a first level in response to said first output signal; and means for providing said digital output signal with a second level in response to said second output signal thereby to provide a reproduction of said received data words.
Claim 5
Dependent Claim 59 words
The system of claim 3 further including: means responsive to the interval between transitions in said recovered signal for providing a third signal in response to the interval between transitions exceeding the period between bits; and means responsive to said third signal for providing a separation in said digital output signal thereby to define framing for said data words.
Claim 6
Dependent Claim 220 words
A data system for providing self-clocking digital representatIons of data words to a data channel comprising: means for receiving said data words at a particular data pulse rate; means for generating a clock signal related to said data pulse rate; means responsive to said clock signal for providing a first timing signal having a predetermined phase relationship to said data pulse rate; means operating in response to said clock signal for providing a second timing signal substantially out of phase with said first timing signal; means operative to determine coincidence between said first timing signal and a first binary state in said received data words to provide a first gating signal; means for combining said first gating signal and said second timing signal to provide a second gating signal; means operative in response to said clock signal to provide frame signal pulses with an interval between pulses corresponding to the interval between data words; means for producing a binary signal having transitions responsive to pulses in said second gating signal; means operative in response to said frame signal pulses for inhibiting transitions in said binary signal for a predetermined interval greater than the period between pulses in said received data words and in synchronism with said frame signal pulses; and means for applying said binary signal to said data channel.
Claim 7
Dependent Claim 220 words
A data system for providing self-clocking digital representatIons of data words to a data channel comprising: means for receiving said data words at a particular data pulse rate; means for generating a clock signal related to said data pulse rate; means responsive to said clock signal for providing a first timing signal having a predetermined phase relationship to said data pulse rate; means operating in response to said clock signal for providing a second timing signal substantially out of phase with said first timing signal; means operative to determine coincidence between said first timing signal and a first binary state in said received data words to provide a first gating signal; means for combining said first gating signal and said second timing signal to provide a second gating signal; means operative in response to said clock signal to provide frame signal pulses with an interval between pulses corresponding to the interval between data words; means for producing a binary signal having transitions responsive to pulses in said second gating signal; means operative in response to said frame signal pulses for inhibiting transitions in said binary signal for a predetermined interval greater than the period between pulses in said received data words and in synchronism with said frame signal pulses; and means for applying said binary signal to said data channel.
Claim 8
Dependent Claim 151 words
The data system of claim 5 further including: means for recovering the signal applied to said data channel; means for detecting peak amplitudes in said recovered signal; means for generating a pulse in response to each detected amplitude peak; means for generating a first interval having a duration intermediate 50 percent and 100 percent of the shortest period between pulses in said received data words at said particular rate; means for producing a first control signal in response to generated pulses subsequent to the running of said first interval; means for triggering said first interval in response to said first control signal; means for producing a second control signal in response to generated pulses occurring during the running of said interval; and means for producing a binary output signal having a first level in response to said first control signal and a second level in response to said second control signal.
Claim 9
Dependent Claim 115 words
The data system of claim 6 further including: means for generating a medical analog signal representative of body processes; means operative in response to said frame signal pulses for generating a ramp signal in the interval between said frame signal pulses; means for comparing said medical signal and said ramp signal and operative to provide a compare signal representative of preset relationship in the levels of said two signals; means for counting at a predetermined rate substantially in excess of said data pulse rate in the interval between frame signal pulses and said compare signal; and means for forming said data words to represent the count of said counting means coincident with said compare signal.
Claim 10
Dependent Claim 93 words
The data system of claim 7 further including: means responsive to said generated pulse for producing a second interval having a duration greater than the period between pulses in said received data words; means for providing a third control signal in response to the interval between pulses in said generated pulses exceeding said second interval; a shift register operative to receive said binary output signal at the rate of said first control signal; and buffer register means operative to receive the contents of said shift register in response to said third control signal.
Claim 11
Dependent Claim 54 words
The data system of claim 8 further including: means operative in response to the signal in said buffer register for providing an analog output signal representative of the digital magnitude of said signal in said buffer register; and means for filtering said analog output signal to provide a reproduction Of said medical analog signal.
Claim 12
Dependent Claim 14 words
The data system of claim 9 wherein said channel is a magnetic disk recorder.
Claim 13
Independent Claim 96 words
A method for providing digital signals in a self-clocking format comprising the steps of: receiving said digital signals as binary data words at a known data pulse rate; providing a pulse sequence synchronized to said known data pulse rate; generating a binary signal having transitions of a first set between first and second levels in response to said pulse sequence; detecting a predetermined signal level in the received binary data words; and producing a transition in said binary signal intermediate the transitions of said first set in response to the detection of said predetermined signal level.
Claim 14
Independent Claim 96 words
A method for providing digital signals in a self-clocking format comprising the steps of: receiving said digital signals as binary data words at a known data pulse rate; providing a pulse sequence synchronized to said known data pulse rate; generating a binary signal having transitions of a first set between first and second levels in response to said pulse sequence; detecting a predetermined signal level in the received binary data words; and producing a transition in said binary signal intermediate the transitions of said first set in response to the detection of said predetermined signal level.
Claim 15
Independent Claim 165 words
A system for providing self-clocking data signals comprising: a shift register; means for loading said shift register with a data word; means for generating clock pulses; means for generating a data pulse intermediate each of said clock pulses; means for applying said clock pulses to said shift register to provide a serial data output from said shift register; a gate responsive to said serial data output and said data pulses to provide a coincidence indicating signal in response to simultaneous existence of a data pulse and a predetermined signal level in said serial data output; means for combining said coincidence indicating signal and said clock pulses to provide a self-clocking pulse train; a bistable circuit having first and second stable output levels and an input responsive to pulses to shift the output level of said bistable circuit; and means for applying said self-clocking pulse train to the input of said bistable circuit to provide said self-clocking data signals at the output of said bistable circuit.
Claim 16
Independent Claim 165 words
A system for providing self-clocking data signals comprising: a shift register; means for loading said shift register with a data word; means for generating clock pulses; means for generating a data pulse intermediate each of said clock pulses; means for applying said clock pulses to said shift register to provide a serial data output from said shift register; a gate responsive to said serial data output and said data pulses to provide a coincidence indicating signal in response to simultaneous existence of a data pulse and a predetermined signal level in said serial data output; means for combining said coincidence indicating signal and said clock pulses to provide a self-clocking pulse train; a bistable circuit having first and second stable output levels and an input responsive to pulses to shift the output level of said bistable circuit; and means for applying said self-clocking pulse train to the input of said bistable circuit to provide said self-clocking data signals at the output of said bistable circuit.
Claim 17
Dependent Claim 74 words
The system of claim 12 further including: means for generating a frame pulse to indicate intervals between data words in the serial data output of said shift register; and gating means responsive to said self-clocking pulse train and said frame pulse to block the application of said pulse train to the input of said bistable circuit coincident with said frame pulse for a duration greater than the interval between pulses in said clock pulse.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-06-03 1977-12-03 1978-06-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-06-03 1981-12-03 1982-06-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-06-03 1985-12-03 1986-06-04 $7700.00 Window Closed / Lapsed

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