US3696401A
Expired / Lapsed
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Digital data decoder with data rate recovery
Assignee: Arris Technology Inc
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Filing: 1970-10-09
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Granted: 1972-10-03
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Expires: 1990-10-09
Abstract
Abstract A decoder circuit is disclosed for decoding digital signals having frame end transitions, for example, on bits of value ''''1'''' and mid-frame transitions for the second one of two sequential ''''0''s'''' and for each ''''0'''' thereafter. Sequential transitions alternatingly trigger two oscillators of similar frequency which is at least twice the bit rate frequency. The oscillations overlap to ensure phase coherency. The oscillator outputs are combined and counted down to the bit rate frequency for bit rate recovery. The frame ends are strobed to detect absence or presence of a transition for bit value recovery.
Inventors
- 👤 James T Vance
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 14:50
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1423
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
256 words
A decoder circuit receiving signal representing digital data, wherein the delay between sequential, alternatingly directed transitions in the signal is of digital significance, the data represented in and by the signal having a particular rate, comprising: first and second oscillator means for individually providing oscillations at similar particular frequency when enabled, the frequency being an integral multiple of the data bit rate, so that transitions occurring pursuant to a regular data bit rate coincide with the same phase in either oscillator when oscillating; third means connected to receive the data representing signal, and connected to the first and second oscillator means respectively to start the first oscillator means in response to transitions in the first direction and at a particular phase of the oscillations, and to start the second oscillator means in response to transitions in the second direction and at the same particular phase, the first and second means after a transition in the second and first directions; fourth means connected to the first and second oscillator means to obtain a combined output as clock pulse train; and fifth means connected to the fourth means to obtain a counting operation of the clock pulses in phase synchronism with the transitions, including sixth means providing a signal train that is representative of the bit rate, and including seventh means responsive to the counting operation to detect relative occurrence and non-occurrence of the transitions in relation to the progressing phase of bit presentation at said bit rate by said digital signal irrespective of direction of the transitions.
Claim 2
Dependent Claim
256 words
A decoder circuit receiving signal representing digital data, wherein the delay between sequential, alternatingly directed transitions in the signal is of digital significance, the data represented in and by the signal having a particular rate, comprising: first and second oscillator means for individually providing oscillations at similar particular frequency when enabled, the frequency being an integral multiple of the data bit rate, so that transitions occurring pursuant to a regular data bit rate coincide with the same phase in either oscillator when oscillating; third means connected to receive the data representing signal, and connected to the first and second oscillator means respectively to start the first oscillator means in response to transitions in the first direction and at a particular phase of the oscillations, and to start the second oscillator means in response to transitions in the second direction and at the same particular phase, the first and second means after a transition in the second and first directions; fourth means connected to the first and second oscillator means to obtain a combined output as clock pulse train; and fifth means connected to the fourth means to obtain a counting operation of the clock pulses in phase synchronism with the transitions, including sixth means providing a signal train that is representative of the bit rate, and including seventh means responsive to the counting operation to detect relative occurrence and non-occurrence of the transitions in relation to the progressing phase of bit presentation at said bit rate by said digital signal irrespective of direction of the transitions.
Claim 3
Dependent Claim
75 words
In a decoder circuit as in claim 1, the third means including means (a) providing an enabling signal to the first means from each transition in the first direction up to a small delay after the respective next transition in the second direction; and including means (b), providing an enabling signal to the second means from each transition in the second direction to a small delay after the respective next transition in the first direction.
Claim 4
Dependent Claim
70 words
In a decoder circuit as in claim 1, wherein transitions in either direction occur on bit frame boundaries in representation of bits of a first value, and wherein transitions in either direction occur in center frame positions for each second sequential bit of a second value and for each bit of second value immediately thereafter, the oscillations having frequency that is an even numbered multiple of the bit rate frequency.
Claim 5
Dependent Claim
233 words
A decoder circuit receiving signal representing digital data wherein a particular characteristic may occur on bit frame boundaries of the data and in the center of a frame, whereby the delay between sequential ones of the particular characteristics is of digital significance, the combination comprising: first means for providing oscillations at a particular frequency that is an even numbered multiple of the bit frame rate; second means connected to receive the data representing signal, being responsive to the particular characteristic and connected to the first means to establish a particular phase of the oscillations with each occurrence of that particular characteristic; third means connected to the first means for obtaining a couNting operation of the oscillations on a cyclic repetitive basis as to each bit frame boundary irrespective of occurrence of particular characteristic; fourth means connected to the first and third means for detecting occurrence and non-occurrence of the particular characteristic on bit frame boundaries and providing signal representation of the corresponding digital significance thereof; and counter means connected to the first means and to the second means to be responsive to a delay counting of oscillations in between occurrence of two sequential particular characteristics which delay is representative of occurrence of at least a particular one of the two occurrences on a bit frame boundary, and connected to the third means to obtain synchronization of the counting operation by the third means.
Claim 6
Dependent Claim
233 words
A decoder circuit receiving signal representing digital data wherein a particular characteristic may occur on bit frame boundaries of the data and in the center of a frame, whereby the delay between sequential ones of the particular characteristics is of digital significance, the combination comprising: first means for providing oscillations at a particular frequency that is an even numbered multiple of the bit frame rate; second means connected to receive the data representing signal, being responsive to the particular characteristic and connected to the first means to establish a particular phase of the oscillations with each occurrence of that particular characteristic; third means connected to the first means for obtaining a couNting operation of the oscillations on a cyclic repetitive basis as to each bit frame boundary irrespective of occurrence of particular characteristic; fourth means connected to the first and third means for detecting occurrence and non-occurrence of the particular characteristic on bit frame boundaries and providing signal representation of the corresponding digital significance thereof; and counter means connected to the first means and to the second means to be responsive to a delay counting of oscillations in between occurrence of two sequential particular characteristics which delay is representative of occurrence of at least a particular one of the two occurrences on a bit frame boundary, and connected to the third means to obtain synchronization of the counting operation by the third means.
Claim 7
Dependent Claim
187 words
A decoder circuit receiving signal representing digital data wherein a particular characteristic may occur on bit frame boundaries of the data and in the center of a frame, whereby the delay between sequential ones of the particular characteristics is of digital significance, the combination comprising: first and second oscillators connected to receive the data representing signals and being alternatingly stimulated in response to occurrence of a particular characteristic up to the respective next one, each oscillator having similar frequency that is an even numbered multiple of the bit frame rate and commencing at a precise phase; combining means connected to the oscillators to provide a common clock pulse train with corrected phase on each recurring particular characteristic; first means connected to the combining means for obtaining a counting operation of the oscillations on a cyclic repetitive basis as to each bit frame boundary irrespective of occurrence of particular characteristic; and second means connected to the first means and to the first and second oscillators for detecting occurrence and non-occurrence of the particular characteristic on bit frame boundaries and providing signal representation of the corresponding digital significance thereof.
Claim 8
Dependent Claim
187 words
A decoder circuit receiving signal representing digital data wherein a particular characteristic may occur on bit frame boundaries of the data and in the center of a frame, whereby the delay between sequential ones of the particular characteristics is of digital significance, the combination comprising: first and second oscillators connected to receive the data representing signals and being alternatingly stimulated in response to occurrence of a particular characteristic up to the respective next one, each oscillator having similar frequency that is an even numbered multiple of the bit frame rate and commencing at a precise phase; combining means connected to the oscillators to provide a common clock pulse train with corrected phase on each recurring particular characteristic; first means connected to the combining means for obtaining a counting operation of the oscillations on a cyclic repetitive basis as to each bit frame boundary irrespective of occurrence of particular characteristic; and second means connected to the first means and to the first and second oscillators for detecting occurrence and non-occurrence of the particular characteristic on bit frame boundaries and providing signal representation of the corresponding digital significance thereof.
Claim 9
Dependent Claim
27 words
In a decoder as in claim 5, each oscillator remaining stimulated a short period beyond stimulation of the respective other one to establish similar overlapping oscillation phases.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-03 | 1976-04-03 | 1976-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-03 | 1980-04-03 | 1980-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-03 | 1984-04-03 | 1984-10-03 | $7700.00 | Window Closed / Lapsed |