Programmable circuit {13 {11 the method of programming thereof and the devices so programmed

Claim 2

A silicon semiconductor diode having a P-region and an Nregion, said regions being separated by a P-N junction, a first electrical contact made to said P-region by a layer of metal to an area of said P-region and a second electrical contact made to said N-region by a layer of metal to an area of said N-region, said semiconductor diode being protected by at least one more protective coating over the surface of the otherwise exposed semiconductor diode wherein the distance between said electrical contacts is predetermined with respect to each other that upon the passage of a given current pulse through the P-N junction in the reverse direction, said electrical contacts may be caused to melt and to flow thereby forming upon solidification a permanent metallic bridge between said P-N junction.

Claim 3

The diode of claim 1 wherein the electrical contacts are aluminum.

Claim 4

The diode of claim 2 wherein said P-region is comprised of a first P-region and a second P-region, said second P-region being more heavily doped and of a substantially higher conductivity than said first P-region and further being substantially localized to the surface of said semiconductor diode is a relatively narrow strip extending from said electrical contact for said first P-region to said P-N junction.

Claim 5

A semiconductor diode on an N-type semiconductor wafer with a P-region formed by the diffusion of a P-type impurity into said wafer in a selected area of said wafer and a second N-region formed on the surface of said P-type region by the diffusion of an N-type impurity into a selected area of said P-region, thereby forming a P-N junction between said P-region and said second N-region, electrical contact made to said N-type wafer by a first layer of metal, electrical contact made to said P-region by a second layer of metal to an area of said P-region, electrical contact made to said second N-region by a third layer of metal to an area of said second N-region, said semiconductor diode being protected by at least one protective coating over the surface of the otherwise exposed semiconductor diode, wherein said second layer of metal and said third layer of metal are so arranged with respect to each other than upon the passage of a current pulse through the P-N junction in the reverse direction, said electrical contacts may be caused to melt and to flow thereby forming, upon solidification, a permanent metallic bridge between said P-N junction.

Claim 6

A semiconductor diode on an N-type semiconductor wafer with a P-region formed by the diffusion of a P-type impurity into said wafer in a selected area of said wafer and a second N-region formed on the surface of said P-type region by the diffusion of an N-type impurity into a selected area of said P-region, thereby forming a P-N junction between said P-region and said second N-region, electrical contact made to said N-type wafer by a first layer of metal, electrical contact made to said P-region by a second layer of metal to an area of said P-region, electrical contact made to said second N-region by a third layer of metal to an area of said second N-region, said semiconductor diode being protected by at least one protective coating over the surface of the otherwise exposed semiconductor diode, wherein said second layer of metal and said third layer of metal are so arranged with respect to each other than upon the passage of a current pulse through the P-N junction in the reverse direction, said electrical contacts may be caused to melt and to flow thereby forming, upon solidification, a permanent metallic bridge between said P-N junction.

Claim 7

The diode of claim 4 wherein the N-type wafer has a N+ layer formed on the surface of said N-type wafer opposite the surface on which the P-N junction was formed, said N+ layer being located between said N-type wafer and said deposited first layer of metal.

Claim 12

A programmable memory cell comprised of a transistor having an emitter, a base and a collector and a semiconductor diode containing a P-region, an N-region and a P-N junction, said diode being coupled to one of said emitter and said collector of said transistor so that current in the reverse direction through said diode may be controlled by the voltage on said base, said transistor having a sufficient current carrying capacity to conduct current sufficient to destructively effect said diode.

Claim 13

A programmable memory cell comprised of a transistor having an emitter, a base and a collector and a semiconductor diode containing a P-region, an N-region and a P-N junction, said diode being coupled to one of said emitter and said collector of said transistor so that current in the reverse direction through said diode may be controlled by the voltage on said base, said transistor having a sufficient current carrying capacity to conduct current sufficient to destructively effect said diode.

Claim 14

The memory element of claim 8 wherein saiD transistor is a NPN transistor and said N-region of said diode is electrically connected to said emitter of said transistor.

Claim 15

The memory element of claim 9 wherein said semiconductor diode has a P-region and an N-region, said regions being separated by a P-N junction, a first electrical contact made to said P-region by a layer of aluminum to an area of said P-region and a second electrical contact made to said N-region by a layer of aluminum to an area of said N-region, said semiconductor diode being protected by at least one more protective coating over the surface of the otherwise exposed semiconductor diode wherein the distance between said electrical contacts is predetermined with respect to each other that upon the passage of a given current pulse through the P-N junction in the reverse direction, said electrical contacts may be caused to melt and to flow thereby forming upon solidification a permanent metallic bridge between said P-N junction, and said semiconductor diode and said transistor are of monolithic construction.

Claim 16

A circuit element comprised of a P-type semiconductor region and an N-type semiconductor region, an electrical contact formed by a layer of metal to an area of said P-type region, a second electrical contact formed by a layer of metal to an area of said N-type region, and at least one protective coating over the surface of the otherwise exposed semiconductor diode, said P type and N type regions being electrically connected by a conductive bridge on the surface of said semiconductor regions formed by the melting and flowing of said contacts.

Claim 17

A circuit element comprised of a P-type semiconductor region and an N-type semiconductor region, an electrical contact formed by a layer of metal to an area of said P-type region, a second electrical contact formed by a layer of metal to an area of said N-type region, and at least one protective coating over the surface of the otherwise exposed semiconductor diode, said P type and N type regions being electrically connected by a conductive bridge on the surface of said semiconductor regions formed by the melting and flowing of said contacts.

Claim 18

The circuit element of claim 11 wherein said P-region is comprised of a first P-region and a second P-region, said second P-region being more heavily doped and of substantially higher conductivity than said first P-region and further being substantially localized to the surface of said first P-region in a relatively narrow strip extending from said electrical contact for said first P-region to said N-region.

Claim 19

A circuit comprised of the circuit element of claim 11 disposed in the same body of semiconductor material and connected in series with a NPN transistor having an emitter, a base and a collector, said electrical contact to said N-region of said circuit element being electrically coupled to said emitter of said transistor.

Claim 20

A circuit comprised of the circuit element of claim 12 disposed in the same body of semiconductor material and connected in series with a NPN transistor having an emitter, a base and a collector, said electrical contact to said N-region of said circuit element being electrically connected to said emitter of said transistor.

Claim 21

A programmable memory circuit comprised of a transistor having an emitter, a base and a collector and at least one P-N junction, said P-N junction being coupled to one of said emitter and said collector of said transistor so that current in the reverse direction through said P-N junction may be controlled by the voltage on said base, said transistor having a sufficient current carrying capacity to conduct current sufficient to destructively effect said P-N junction.

Claim 22

A programmable memory circuit comprised of a transistor having an emitter, a base and a collector and at least one P-N junction, said P-N junction being coupled to one of said emitter and said collector of said transistor so that current in the reverse direction through said P-N junction may be controlled by the voltage on said base, said transistor having a sufficient current carrying capacity to conduct current sufficient to destructively effect said P-N junction.

Claim 25

A programmable memory circuit comprised of a transistor having an emitter, a base and a collector and at least one P-N junctIon having rectifying characteristics, said P-N junction being coupled to said to said transistor so that current may be caused to flow through said emitter and said collector of said transistor and in the reverse direction through said P-N junction, said transistor having a sufficient current carrying capacity to conduct current sufficient to destructively effect said P-N junction.

Claim 26

A programmable memory circuit comprised of a transistor having an emitter, a base and a collector and at least one P-N junctIon having rectifying characteristics, said P-N junction being coupled to said to said transistor so that current may be caused to flow through said emitter and said collector of said transistor and in the reverse direction through said P-N junction, said transistor having a sufficient current carrying capacity to conduct current sufficient to destructively effect said P-N junction.

Claim 27

The memory circuit of claim 17 wherein said P-N junction is between a P-region and an N-region, at least one of said regions having metal contact thereto electrically coupled in series with said P-N junction, whereby the rectifying characteristics of said P-N junction may be destructively effected, at least in part, by the partial migration of said metal contact.