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US3801905A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of testing for the operability of integrated semiconductor circuits having a plurality of separable circuits

Assignee: International Business Machines Corp
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Filing: 1973-05-29
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Granted: 1974-04-02
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Expires: 1993-05-29
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Abstract

Abstract A method for determining whether an integrated circuit chip containing a plurality of separable circuits is operable when one or more of the separable circuits is not functional. A chip including a plurality of discrete or separable circuits, each of which include means for selectively receiving and distributing a voltage level necessary to render the particular circuit operable, the chip further including a region of one type conductivity at said voltage level common to all of the discrete circuits is tested by a method which will insure that shortcircuits between a particular circuit found not to be functional and therefore not to be rendered operable and the common region will not inadvertently apply the voltage level from the common region to voltage receiving and distribution means in the nonfunctional circuit. All the discrete circuits are first tested to determine which are functional. Then these circuits which fail the functionality test are tested further to detect whether any of these failed circuits have electrical short-circuits between the common region and the means for receiving and distributing said operable voltage level in the failed circuit. If any of the failed circuits have such a short, the chip is considered to be inoperative because such a short will inadvertently connect the failed circuit with the functional circuits.

Inventors

  • 👤 T Baker
  • 👤 M Chafghaichi
  • 👤 R Stevens
  • 👤 D Tuman

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 21:54
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2273; H; H10; H10D; H10D84/00; H10D84/90; H10D84/901

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 137 words
In a method of testing for the functionality of one or more of a plurality of discrete circuits in an integrated semiconductor circuit structure wherein each of said circuits includes means for selectively receiving and distributing a voltage level necessary to render said circuit operable, said structure including means for selectively applying said voltage level to one or more of said circuits and wherein said structure includes a region of one type conductivity at said voltage level common to all of said discrete circuits, the steps comprising: testing each of said discrete circuits to determine which circuits are functional, and testing said circuits which fail the functionality test to detect whether any of said failed circuits have electrical short-circuits connecting said common region to the means for receiving and distributing said voltage level in said failed circuit.
Claim 2
Dependent Claim 137 words
In a method of testing for the functionality of one or more of a plurality of discrete circuits in an integrated semiconductor circuit structure wherein each of said circuits includes means for selectively receiving and distributing a voltage level necessary to render said circuit operable, said structure including means for selectively applying said voltage level to one or more of said circuits and wherein said structure includes a region of one type conductivity at said voltage level common to all of said discrete circuits, the steps comprising: testing each of said discrete circuits to determine which circuits are functional, and testing said circuits which fail the functionality test to detect whether any of said failed circuits have electrical short-circuits connecting said common region to the means for receiving and distributing said voltage level in said failed circuit.
Claim 3
Dependent Claim 40 words
The method of claim 1 wherein said test for electrical short-circuits comprises maintaining said common region at said voltage level and sensing any resulting change in the level of voltage in said receiving and distributing means of said failed circuit.
Claim 4
Dependent Claim 42 words
The method of claim 1, including the step, subsequent to testing, of selectively applying said voltage level to the circuits which passed the functionality tests only in the absence of detected short-circuits in all of said circuits which failed the functionality tests.
Claim 5
Dependent Claim 30 words
The method of claim 2 wherein said test for short-circuits detects a short-circuit when said resulting change in the level in said receiving and distributing means exceeds a predetermined value.
Claim 6
Dependent Claim 42 words
The method of claim 4 including the step, subsequent to testing, of selectively applying said voltage level to the circuits which passed the functionality tests only in the absence of detected short-circuits in all of said circuits which failed the functionality tests.
Claim 7
Dependent Claim 52 words
The method of claim 1 wherein said test for electrical short-circuits comprises maintaining said common region at said voltage level, applying said voltage level only to circuits which passed the functionality tests and sensing any resulting change in the level of voltage in the receiving and distributing means of the failed circuit.

References Cited (Backward Citations)

US3448392A Cited
US3466544A Cited
US3590378A Cited
US3618201A Cited
US3528104A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-04-01 1977-10-01 1978-04-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-04-01 1981-10-01 1982-04-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-04-01 1985-10-01 1986-04-02 $7700.00 Window Closed / Lapsed

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