US3590378A — Fault-detecting monitor for integrated circuit un…

Claim 1

Independent Claim 246 words

An integrated circuit assembly comprising: a main circuit assembly and a fault-detecting circuit assembly on a unitary substrate, said main circuit assembly including a plurality of check points and input and output circuits and providing output binary values responsive to input signals appearing at said input circuits, said binary values being represented by a first voltage level for one state and a second voltage level of different magnitude for the other state; said fault-detecting circuit assembly including logic means for obtaining a binary check value responsive to signals appearing at said check points, means interconnecting said fault-detecting circuit assembly to predetermined ones of said check points, comparing means for comparing the binary check values against the output binary values of said main circuit; said fault-detecting circuit assembly further including threshold detecting means having inputs connected to predetermined check points of said main circuit assembly, said threshold detecting means being responsive to said inputs to render an output of predetermined binary value when one or more of said inputs of said threshold detecting means assumes a voltage intermediate said first and second voltage levels, memory means for storing the results of the comparison effected by said comparing means, means for communicating the output binary value of said threshold detecting means to said memory means, said memory retaining the information received from said threshold detecting means for a predetermined period of time, and means for signaling the contents of said memory means external to said integrated circuit assembly.

Claim 2

Dependent Claim 246 words

An integrated circuit assembly comprising: a main circuit assembly and a fault-detecting circuit assembly on a unitary substrate, said main circuit assembly including a plurality of check points and input and output circuits and providing output binary values responsive to input signals appearing at said input circuits, said binary values being represented by a first voltage level for one state and a second voltage level of different magnitude for the other state; said fault-detecting circuit assembly including logic means for obtaining a binary check value responsive to signals appearing at said check points, means interconnecting said fault-detecting circuit assembly to predetermined ones of said check points, comparing means for comparing the binary check values against the output binary values of said main circuit; said fault-detecting circuit assembly further including threshold detecting means having inputs connected to predetermined check points of said main circuit assembly, said threshold detecting means being responsive to said inputs to render an output of predetermined binary value when one or more of said inputs of said threshold detecting means assumes a voltage intermediate said first and second voltage levels, memory means for storing the results of the comparison effected by said comparing means, means for communicating the output binary value of said threshold detecting means to said memory means, said memory retaining the information received from said threshold detecting means for a predetermined period of time, and means for signaling the contents of said memory means external to said integrated circuit assembly.

Claim 3

Dependent Claim 234 words

An integrated circuit assembly comprising a main circuit and an auxiliary fault-detecting circuit, both of said circuits being disposed on a unitary chip, said main circuit being connected to receive a plurality of binary input signals and responsive thereto to generate a binary output signal representing the binary result of a predetermined logical operation performed on said binary input signals by said main circuit, said fault-detecting circuit comprising circuit elements having a slower speed of response than the circuit elements of said main circuit, said fault-detecting circuit being connected to receive a plurality of binary signals present in said main circuit and responsive to the binary signals received thereby to generate an output fault signal at an output point thereof when said binary signals received thereby fail to satisfy a predetermined criterion for the proper operation of said main circuit, memory means disposed on said chip coupled to said outPut point and responsive to the occurrence of said fault signal for storing a fault indicium and for delivering an output signal representing said stored fault indicium, said memory means being provided with a reset terminal coupled to receive a stimulus generated external to said chip for clearing said fault indicium from said memory means, said memory means maintaining each fault indicium stored thereby until said stimulus is received, an output lead for said chip, and means for coupling said output lead to said memory

Claim 4

Dependent Claim 234 words

An integrated circuit assembly comprising a main circuit and an auxiliary fault-detecting circuit, both of said circuits being disposed on a unitary chip, said main circuit being connected to receive a plurality of binary input signals and responsive thereto to generate a binary output signal representing the binary result of a predetermined logical operation performed on said binary input signals by said main circuit, said fault-detecting circuit comprising circuit elements having a slower speed of response than the circuit elements of said main circuit, said fault-detecting circuit being connected to receive a plurality of binary signals present in said main circuit and responsive to the binary signals received thereby to generate an output fault signal at an output point thereof when said binary signals received thereby fail to satisfy a predetermined criterion for the proper operation of said main circuit, memory means disposed on said chip coupled to said outPut point and responsive to the occurrence of said fault signal for storing a fault indicium and for delivering an output signal representing said stored fault indicium, said memory means being provided with a reset terminal coupled to receive a stimulus generated external to said chip for clearing said fault indicium from said memory means, said memory means maintaining each fault indicium stored thereby until said stimulus is received, an output lead for said chip, and means for coupling said output lead to said memory

Claim 5

Dependent Claim 123 words

The integrated circuit assembly of claim 2, wherein said binary signals comprise a first voltage level for representing one binary value and a second voltage level for representing the other binary value, wherein said fault-detecting circuit further comprises a threshold detecting means connected to receive predetermined binary signals present in said main circuit, said threshold detecting means being responsive to the binary signals received thereby to generate an output signal when at least one of said binary signals received thereby assumes a voltage intermediate said first and second voltage levels, and wherein means is provided for coupling said memory means to said threshold detecting means for storing in said memory means a fault indicium when said threshold detecting means output signal is generated.

Claim 6

Dependent Claim 110 words

The integrated circuit assembly of claim 2, wherein said fault-detecting circuit comprises a logic unit and comparing means, said logic unit being connected to receive said binary input signals received by the main circuit and responsive to the binary signals received thereby to generate a binary check signal corresponding to the binary output signal generated by said main circuit when said main circuit is properly operative, said comparing means being coupled to receive said binary check signal and the binary output signal generated by said main circuit, said comparing means delivering said output fault signal when said binary output signal received thereby fails to correspond to said binary check signal.

Claim 7

Dependent Claim 123 words

The integrated circuit assembly of claim 4, wherein said binary signals comprise a first voltage level for representing one binary value and a second voltage level for representing the other binary value, wherein said fault-detecting circuit further comprises a threshold detecting means connected to receive predetermined binary signals present in said main circuit, said threshold detecting means being responsive to the binary signals received thereby to generate an output signal when at least one of said binary signals received thereby assumes a voltage intermediate said first and second voltage levels, and wherein means is provided for coupling said memory means to said threshold detecting means for storing in said memory means a fault indicium when said threshold detecting means output signal is generated.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1974-06-28	1974-12-28	1975-06-29	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1978-06-28	1978-12-28	1979-06-29	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1982-06-28	1982-12-28	1983-06-29	$7700.00	Window Closed / Lapsed

Fault-detecting monitor for integrated circuit units

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