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Patent EP0704895A2 successfully refreshed from Google Patents.
EP0704895A2
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EP
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Process for manufacturing semiconductor device and semiconductor wafer
Assignee: NEC Electronics Corp
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Filing: 1995-10-02
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Granted: —
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Expires: 2015-10-02
Abstract
Abstract There is provided a process for manufacturing a semiconductor device. Chip sections 10a are defined on a wafer 10 by scribe lines 13 with each chip section 10a having chip electrodes 11 formed thereon. The wafer 10 is covered with a passivating film 12 except for on the chip electrodes 11. Aluminum interconnection layers 60 are provided such that each layer 60 is connected to the chip electrode 11 at one end thereof and the other end of the layer 60 is extended towards the central portion of the chip section 10a. A cover coating film 64 is applied on the passivating film 12 and the layers 60. A number of apertures 66 are formed in the coating film 64 passing therethrough, and bump electrodes 70 are formed at the position corresponding to the apertures 66. The chip sections 10a are then separated from each other along the scribe lines 13 into semiconductor devices 80.
Inventors
- 👤 Keiichiro Kata
- 👤 Shinichi Chikaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 14:57
CPC Classifications
H; H10; H10P; H10P54/00; H10W; H10W72/00; H10W72/01; H10W72/012; H10W70/00; H10W70/01; H10W70/05; H10W72/019; H10W72/071; H10W72/073; H10W72/20; H10W72/241; H10W72/244; H10W72/251; H10W72/252; H10W72/90; H10W72/921; H10W72/922; H10W72/923; H10W72/951; H10W72/952
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
133 words
A process for manufacturing a semiconductor device comprising the step of defining a number of semiconductor chip sections (10a) on a wafer (10), each semiconductor chip section having a number of chip electrodes (11) formed on one surface, characterised by further comprising the steps of: forming a number of interconnections (60) on the wafer for each semiconductor chip section such that each interconnection is connected to the chip electrode at one end thereof and is extended inwardly of the chip section at the other end; forming on the entire surface of the wafer a cover coating film (64) having a number of apertures (66) at positions corresponding to the interconnections; forming bump terminals connected to the interconnections through said apertures; and separating the semiconductor chip sections on the wafer as individual semiconductor chips.
Claim 2
Dependent Claim
168 words
A process for manufacturing a semiconductor device comprising the step of defining a number of semiconductor chip sections (10a) on a wafer (10), each semiconductor chip section having a number of chip electrodes (11) formed on one surface along a periphery thereof, the one surface being covered with a passivating film (12) except for the positions where the chip electrodes are formed, characterised by further comprising the steps of: forming a number of interconnection layers (60) on the wafer for each semiconductor chip section such that each interconnection layer is connected to the chip electrode at one end thereof and is extended inwardly of the chip section at the other end; forming on the entire surface of the wafer a cover coating film (64); forming a number of apertures (66) in the cover coating film, the apertures being formed into a matrix; forming a number of bumps (70) on the respective apertures; and separating the semiconductor chip sections on the wafer as individual semiconductor chips along scribe lines.
Claim 3
Dependent Claim
34 words
A process for manufacturing a semiconductor device as claimed in Claim 2, characterised in that the interconnection layer is extended inward where the semiconductor chip section is exposed to the atmosphere through the aperture.
Claim 4
Dependent Claim
24 words
A process for manufacturing a semiconductor device as claimed in claim 2, characterised in that the bumps are formed away from the scribe line.
Claim 5
Dependent Claim
29 words
A process for manufacturing a semiconductor device as claimed in claim 2, characterised in that the bumps are formed at the position except for just over the chip electrodes.
Claim 6
Dependent Claim
37 words
A semiconductor wafer (10) having a number of semicenductor chips, characterised by comprising bump electrodes (70) formed into a matrix on an entire surface of the wafer except for on scribe lines (13) between the semiconductor chips.
Claim 7
Dependent Claim
154 words
A process for manufacturing a semiconductor device having a number of chip electrodes (11), a number of bump electrodes (70), and interconnecting layers (60) for electrically connecting the chip electrode and the bump electrode, characterised by comprising the steps of: providing a wafer (10) having a number of chip sections (10a) defined thereon by scribe lines (13), each chip section having the chip electrodes formed thereon; providing the interconnection layers such that each interconnection layer is connected to the chip electrode at one end thereof and the other end of the interconnection layer is extended towards the central portion of the chip section; applying a coating film (64) over the entire surface of the wafer and the interconnection layers; forming a number of apertures (66) in the coating film passing therethrough; forming the bump electrodes at the position corresponding to the apertures; and separating the chip sections from each other along the scribe lines.
Claim 8
Dependent Claim
20 words
A process for manufacturing a semiconductor device as claimed in claim 7, characterised in that the chip section is rectangular.
Claim 9
Dependent Claim
27 words
A process for manufacturing a semiconductor device as claimed in claim 7, characterised in that the interconnection layer extends to the position where the aperture is formed.
Claim 10
Dependent Claim
28 words
A process for manufacturing a semiconductor device as claimed in claim 7, characterised in that the bump electrodes are not located in vertical registration with the chip electrodes.
Claim 11
Dependent Claim
45 words
A semiconductor wafer (10) characterised by having a number of chip sections (10a) defined thereon by scribe lines (13), each chip section having bump electrodes (70) formed thereon, the scribe lines provide for the separation of respective chip sections without division of individual bump electrodes.
Claim 12
Dependent Claim
24 words
A semiconductor wafer (10) characterised by having a number of chip sections (10a) defined thereon each chip section having bump electrodes (70) formed thereon.
References Cited (Backward Citations)
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