§
Luxuse
Patent Intelligence
Sign In
Patent EP0387461A1 successfully refreshed from Google Patents.
← Back to Patent Explorer
EP0387461A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Improved BICMOS logic circuit with full swing operation

Assignee: International Business Machines Corp
•
Filing: 1989-03-14
•
Granted: —
•
Expires: 2009-03-14
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract According to the present invention, a CMOS interface circuit (C2) similar to a latch made by two CMOS cross coupled inverters (INV1, INV2) is placed directly on the output node (14) of conventional BICMOS logic circuit (11) operating alone in a partial swing mode. This latch is made of four FETs P5, P6, N8, N9 cross-coupled in a con­ventional way with the feedback loop connected to said output node (14) The partial voltage swing (VBE to VH-VBE) naturally given by the output bipolar transistors (T1, T2) mounted in an push pull configuration is rein­forced to full swing (GND to VH) by the latch at the end of each transition The state of the output node is forced by the latch because of the high driving capability due to the presence of said output bipolar transistors (T1, T2). As a result, the improved BICMOS logic circuit (D2) has an output signal (S) that ranges within the desired full swing voltage at the output terminal (15). It is a charac­teristic of this embodiment that the structure of CMOS interface circuit (C2) is always independent of the logic function implemented in the conventional BICMOS logic circuit (11). More generally, the CMOS interface circuit may have various physical implementations, however, it is always comprised of CMOS FETs and it becomes active at least in one of the GND to VBE or (VH - BE) to VH range.

Inventors

  • 👤 Gérard Boudon
  • 👤 Ieng Ong
  • 👤 Pierre Mollier
  • 👤 Pascal Tannhof
  • 👤 Jean-Paul Nuez
  • 👤 Franck Wallart

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-05 13:53
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/0136; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K5/00; H03K5/003; H03K5/007

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 147 words
An improved BICMOS logic circuit (D1, ...) having full swing operation of the kind including: a conventional BICMOS logic circuit (11, ...) biased between first and second supply voltages (VH, GND) comprising a logic gate block (13) driven by a plu­rality of logic input signals (A1, A2, ...), and a driving block (12) connected in series with the said logic gate block provided with at least one bipolar transistor (T1, ...); an output terminal (15) con­nected to an output node (14) fed by the said bipolar transistor where the circuit output signal (S) is available; the said conventional BICMOS logic circuit operating normally in a partial swing mode, characterized in that it further includes: an interface circuit means (C) connected to said output terminal to force the said output signal (S) to full swing to give to the said improved BICMOS logic circuit the desired CMOS compatibility.
Claim 2
Dependent Claim 147 words
An improved BICMOS logic circuit (D1, ...) having full swing operation of the kind including: a conventional BICMOS logic circuit (11, ...) biased between first and second supply voltages (VH, GND) comprising a logic gate block (13) driven by a plu­rality of logic input signals (A1, A2, ...), and a driving block (12) connected in series with the said logic gate block provided with at least one bipolar transistor (T1, ...); an output terminal (15) con­nected to an output node (14) fed by the said bipolar transistor where the circuit output signal (S) is available; the said conventional BICMOS logic circuit operating normally in a partial swing mode, characterized in that it further includes: an interface circuit means (C) connected to said output terminal to force the said output signal (S) to full swing to give to the said improved BICMOS logic circuit the desired CMOS compatibility.
Claim 3
Dependent Claim 43 words
The improved BICMOS logic circuit of claim 1, wherein the said interface circuit means comprises a CMOS logic interface circuit (C1) performing the same logic function as the conventional BICMOS logic circuit and driven by the same logic input signals (A1, A2, ...).
Claim 4
Dependent Claim 36 words
The improved BICMOS logic circuit of claim 2 the said driving block (12) comprises two bipolar transistors (T1, T2), so called top and bottom output transis­tors, connected in series with said output node (14) connected therebetween.
Claim 5
Dependent Claim 25 words
The improved BICMOS logic circuit of claim 3, wherein the said conventional BICMOS logic circuit is of the Multi Base type (11′ Figs. 8, 9).
Claim 6
Dependent Claim 23 words
The improved BICMOS logic circuit of claim 3, wherein the said conventional BICMOS logic circuit is of the ICL type (11˝ Fig. 10).
Claim 7
Dependent Claim 40 words
The improved BICMOS logic circuit of claim 3 wherein the said logic gate block (13) comprises an upper part circuit (13a) to drive the said top bipolar transistor and a lower part circuit (13b) to drive said bottom bipolar transistor.
Claim 8
Dependent Claim 24 words
The improved BICMOS logic circuit of claim 6 wherein the said CMOS interface circuit (C1) is the duplica­tion of said upper part circuit (13a).
Claim 9
Dependent Claim 64 words
The improved BICMOS logic circuit of any of above claims 2 to 7 wherein the said first supply voltage is a positive voltage VH and the said second supply voltage is the ground GND and wherein the said CMOS logic interface circuit is comprised of CMOS FETs that become active at least in one of the GND to VBE and (VH-VBE) to VH ranges.
Claim 10
Dependent Claim 46 words
The improved BICMOS logic circuit of claim 1 wherein the said interface circuit means consists of a CMOS logic interface circuit (C2, C2′) comprises two cross coupled inverters (INV1, INV2) forming a latch, the feed back loop of which is connected to said output node (14).
Claim 11
Dependent Claim 38 words
The improved BICMOS logic circuit of claim 10 wherein the said driving block (12) comprises two bipolar transistors (T1, T2) so called top and bottom output transistors connected in series with the said output node (14) connected therebetween.
Claim 12
Dependent Claim 25 words
The improved BICMOS logic circuit of claim 10, where­in the said conventional BICMOS logic circuit is of the Multi Base type (11′ Figs. 8, 9).
Claim 13
Dependent Claim 23 words
The improved BICMOS logic circuit of claim 10, where­in the said conventional BICMOS logic circuit is of the ICL type (11˝ Fig. 10).
Claim 14
Dependent Claim 66 words
The improved BICMOS logic circuit of claim 10 wherein the two CMOS FETs (P6, N9) forming one of said in­verter (INV2), are split into different locations of the improved BICMOS logic circuit: one PFET (P6) is connected in parallel with the base-emitter junction of the top output transistor (T1), the other NFET (N9) is connected in parallel between the base-emit­ter of the bottom output transistor (T2).
Claim 15
Dependent Claim 24 words
The improved BICMOS logic circuit of claim 2 or 9, wherein said conventional BICMOS logic circuit is of half BICMOS type (11‴ Fig. 11).

References Cited (Backward Citations)

EP0058958A2 Cited
US4616146A Cited
EP0254786A1 Cited

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag