Patent EP0210384A1 successfully refreshed from Google Patents.
EP0210384A1
Expired / Lapsed
EP
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Cache memory consistency control with explicit software instructions
Assignee: HP Inc
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Filing: 1986-06-06
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Granted: —
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Expires: 2006-06-06
Abstract
Abstract Memory integrity is maintained in a system with a hierarchical memory using a set of explicit cache control instructions. The caches in the system have two status flags, a valid bit and a dirty bit, with each block of information stored. The operating system executes selected cache control instructions to ensure memory integrity whenever there is a possibility that integrity could be compromised.
Inventors
- 👤 William S. Worley
- 👤 William R. Bryg
- 👤 Allen Baum
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 11:40
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3812; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0804; G06F12/0806; G06F12/0815; G06F12/0837; Y; Y10; Y10S; Y10S707/00; Y10S707/99931; Y10S707/99933; Y10S707/99934
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
168 words
A computer system having a multi-level memory hierarchy and means for maintaining the integrity of the blocks of information stored at different levels in the hierarchy, characterized by a processor (19) for executing instructions and processing data; memory (13) for storing instructions and data; an I/O channel (15) connected to the memory (13) for transferring data and instructions into and out of the memory (13); a cache (21) connected between the processor (19) and the memory (13) for storing selected blocks of information from the memory (13) for use by the processor (19), and having associated with each stored block a valid status flag and a dirty status flag; a set of instructions for providing explicit control of the removal of blocks of data from the cache (21); and an operating sytem capable of causing the execution of certain of the instructions from the instruction set to ensure the consistency of the information stored in the cache (21) with the information transferred into and out of memory (13).
Claim 2
Dependent Claim
168 words
A computer system having a multi-level memory hierarchy and means for maintaining the integrity of the blocks of information stored at different levels in the hierarchy, characterized by a processor (19) for executing instructions and processing data; memory (13) for storing instructions and data; an I/O channel (15) connected to the memory (13) for transferring data and instructions into and out of the memory (13); a cache (21) connected between the processor (19) and the memory (13) for storing selected blocks of information from the memory (13) for use by the processor (19), and having associated with each stored block a valid status flag and a dirty status flag; a set of instructions for providing explicit control of the removal of blocks of data from the cache (21); and an operating sytem capable of causing the execution of certain of the instructions from the instruction set to ensure the consistency of the information stored in the cache (21) with the information transferred into and out of memory (13).
Claim 3
Dependent Claim
85 words
Computer system according to claim 1, characterized in that the instruction set comprises Flush Data Cache, Purge Data Cache, Flush Instruction Cache, Flush Data Cache Entry, Flush Instruction Cache Entry and Synchronize Caches instructions; and in that prior to transfer of data or instructions into or out of memory (13) via the I/O channel (15), the operating system broadcasts the Flush Data Cache and Flush Instruction Cache instructions to the.cache (21) over the range of addresses into which or out of which data is transferred.
Claim 4
Dependent Claim
91 words
Computer system according to claim 2, characterized in that virtual memory (13) is used; in that, when a page or a segment is removed from memory (13), the operating system broadcasts the Flush Data Cache and Flush Instruction Cache instructions to the cache (21) over the range of addresses in the page or segment; and in that, when a page or segment is destroyed, the operating system broadcasts the Purge Data Cache and Flush Instruction Cache instructions to the cache (21) over the range of addresses in the page or segment.
Claim 5
Dependent Claim
111 words
Computer system according to claim 2 or 3, characterized in that the cache (21) is divided into two segments (41,51), a data cache (51) for storing data and an instruction cache (41) for storing instructions; that instructions can be modified when stored as part of a block of data in the data cache (51); and in that after modification of an instruction, the operating system issues the Flush Data Cache instruction to the data cache (51) for the address of the block including the modified instruction, issues the Flush Instruction Cache instruction to the instruction cache (41) for the address of the modified instruction and then executes the Synchronize Caches instruction.
Claim 6
Dependent Claim
53 words
Computer system according to any of claims 2 to 4, characterized in that in the event of a processor failure, the operating system executes a routine including the Flush Data Cache Entry and Flush Instruction Cache Entry instructions over the index range for the data cache (51) and for the instruction cache (41).
References Cited (Backward Citations)
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