EP0145594A2
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EP
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Buffer storage control system
Assignee: Fujitsu Ltd
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Filing: 1984-12-06
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Granted: —
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Expires: 2004-12-06
Abstract
Abstract A buffer storage control system incorporated in a multiprocessor including therein operand side buffer storages and instruction fetch side buffer storages. Under control of the system, a store operation is achieved with the use of an identification flag, which indicates that the related address invalidation is to be effected at the operand side or the instruction fetch side, while a fetch operation is achieved with the use of the identification flag which indicates that the related store address is to be recorded in the operand side buffer memory (TAG) or the instruction fetch side buffer memory (TAG).
Inventors
- 👤 Isao Minamihiyoshi-Danchi 9-104 998 Azuma
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 07:37
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0846; G06F12/0848; G06F12/0806; G06F12/0815; G06F12/0817; G06F12/0822
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
322 words
A buffer storage control system, incorporated in a multiprocessor comprised of a plurality of central processing units, a main storage unit storing many data blocks composed of operand data and instruction data, and a main storage control unit operative to control data transfer between the main storage unit and the central processing units via bus lines. each of the central processing units having a buffer storage unit comprised of a tag part and a data part, the tag part is being separated into an operand (OP) side tag part and an instruction fetch (IF) side tag part, the data part being separated into an OP side data part and an IF side data part, the main storage control unit having'a plurality of buffer storage address memories for each of said central processing units, each of these memories being separated into an OP side memory and an IF side memory, wherein the buffer storage control system is operated with the use of an identification flag which is produced, during a fetch operation, in any one of said central processing units and transferred with an address data for fetch, via a corresponding one of said bus lines, to the main storage control unit, during a fetch operation; the identification flag is also produced, during a store operation, in the main storage control unit and transferred with an address data for invalidation, via a corresponding one of said bus lines, to the central processing unit concerned; said identification flag indicates, during the fetch operation, the address for fetch is to be recorded in said OP side or IF side buffer storage address memory; said identification flag indicates, during the store operation by one of said central processing units, the address for invalidation is to be applied to said OP side or IF side tag part of another central processing unit, so as to invalidate the identical address in the thus indicated side tag part thereof.
Claim 2
Dependent Claim
322 words
A buffer storage control system, incorporated in a multiprocessor comprised of a plurality of central processing units, a main storage unit storing many data blocks composed of operand data and instruction data, and a main storage control unit operative to control data transfer between the main storage unit and the central processing units via bus lines. each of the central processing units having a buffer storage unit comprised of a tag part and a data part, the tag part is being separated into an operand (OP) side tag part and an instruction fetch (IF) side tag part, the data part being separated into an OP side data part and an IF side data part, the main storage control unit having'a plurality of buffer storage address memories for each of said central processing units, each of these memories being separated into an OP side memory and an IF side memory, wherein the buffer storage control system is operated with the use of an identification flag which is produced, during a fetch operation, in any one of said central processing units and transferred with an address data for fetch, via a corresponding one of said bus lines, to the main storage control unit, during a fetch operation; the identification flag is also produced, during a store operation, in the main storage control unit and transferred with an address data for invalidation, via a corresponding one of said bus lines, to the central processing unit concerned; said identification flag indicates, during the fetch operation, the address for fetch is to be recorded in said OP side or IF side buffer storage address memory; said identification flag indicates, during the store operation by one of said central processing units, the address for invalidation is to be applied to said OP side or IF side tag part of another central processing unit, so as to invalidate the identical address in the thus indicated side tag part thereof.
Claim 3
Dependent Claim
98 words
A system as set forth in claim 1, wherein, during said fetch operation, said identification flag is produced from one of said central processing units, each set up with an instruction unit, an execution unit, and a storage control unit, by way of the storage control unit, when the instruction unit issues a request of operand fetch or a request of instruction fetch, together with the related address for fetch, and thereby both the identification flag, indicating OP side fetch or IF side fetch, and the related address for fetch are transferred to the main storage control unit.
Claim 4
Dependent Claim
81 words
A system as set forth in claim 2, wherein each of said OP side memories and each of said IF side memories are provided with an OP side logic gate and an IF side logic gate, either the OP side logic gate or the IF side logic gate being opened in accordance with the identification flag so as to allow the related address for fetch to pass therethrough and record it in the corresponding OP side memory or IF side memory.
Claim 5
Dependent Claim
40 words
A system as set forth in claim 3, wherein said OP side logic gate or said IF side logic gate is opened by a decoder which operates to select one of these logic gates in accordance with the identification flag.
Claim 6
Dependent Claim
77 words
A system as set forth in claim 4, wherein said address for fetch is composed of both upper bits and lower bits, the upper and lower bits passing through the OP side or IF side logic gate opened by said decoder; the lower bits being used for accessing the corresponding memory to specify the address at which the upper bits are recorded; and upper bits specifying the address for fetch in terms of the main storage address.
Claim 7
Dependent Claim
180 words
A system as set forth in claim 1, wherein, during said store operation, the address for store is given from any one of the central processing units, each set up with an instruction unit, an execution unit, and a buffer storage control unit, by way of the storage control unit, so as to store the related store data in the main storage unit at said address for store, while the address for store is applied to the main storage control unit so as to investigate whether the address identical to the address for store exists in any of said OP and IF side memories, by means of comparing circuits provided to individual memories; the comparing circuits commonly receive, at each first input, said address for store, while receive, at the second inputs, respective address data given from individual memories, thereby said identification flag indicative of the OP side or IF side is given, respectively from the OP side comparing circuit or the IF side comparing circuit, if coincidence of the two addresses, at the first and second inputs thereof, occurs.
Claim 8
Dependent Claim
88 words
A system as set forth in claim 6, wherein each of said OP side tag part and each of said IF side tag part are provided with an OP side logic gate and an IF side logic gate, either the OP side logic gate or the IF side logic gate is opened in accordance with the identification flag so as to allow the related address for store to pass therethrough and invalidate the identical address recorded in the corresponding OP side tag part or IF side tag part.
Claim 9
Dependent Claim
81 words
A system as set forth in claim 7, wherein said OP side logic gate or said IF side logic gate is opened by the output from an OP side flip-flop or an IF side flip-flop, the OP side flip-flop is set when said coincidence is detected at the corresponding OP side comparing circuit, and the IF side flip-flop is set when said coincidence is detected at the corresponding IF side comparing circuit, the outputs from these flip-flops forming said identification flag.
Claim 10
Dependent Claim
76 words
A system as set forth in claim 8, wherein said address for store is composed of both upper bits and lower bits; the upper bits specifying the address for store, in terms of the main storage address, and being applied to the first input of each said comparing circuit; the lower bits passing through the opened logic gate and accessing the corresponding OP side or IF side tag part for invalidation of the thus accessed address.
References Cited (Backward Citations)
No citation records indexed.
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