EP0052370A2
Expired / Lapsed
EP
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A virtual storage data processing system
Assignee: Hitachi Ltd
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Filing: 1981-11-16
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Granted: —
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Expires: 2001-11-16
Abstract
Abstract A virtual storage data processing system having an address translation unit (75) shared by a plurality of processors, located in a memory control unit (12) connected to a main memory (10) is disclosed. One of the plurality of processors is a job processor (40) which accesses the main memory with a virtual address to execute an instruction and includes a cache memory (41, 42) which is accessed with a virtual address. One of the plurality of processors is a file processor, (22) which accesses the main memory with a virtual address to transfer data between the main memory and an external memory (20). The cache memory receives the virtual address when the file processor writes to the main memory and if it contains a data block corresponding to the virtual address, it invalidates the corresponding data block. The address translation unit translates the address differently for the access from the file processor and the accesses from other processors.
Inventors
- 👤 Yasushi Fukunaga
- 👤 Tadaaki Bandoh
- 👤 Hidekazu Matsumoto
- 👤 Ryosei Hiraoka
- 👤 Jushi Ide
- 👤 Takeshi Kato
- 👤 Tetsuya Kawakami
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 08:11
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1081; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0833; G06F12/1027; G06F12/1045
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
181 words
1 . A virtual storage data processing system comprising: (a) a main memory (10) for storing programs and data; (b) an external memory (20) for storing programs and data to be stored in said main memory; (c) at least one job processor (40) for accessing said main memory with a virtual address to execute instructions; (d) a file processor (22) for accessing said main memory with a virtual address to transfer programs and data between said main memory and said external memory; (e) at least one cache memory (41, 42) located is said job processor for storing a partial copy of said main memory and accessing said main memory by a virtual memory by said job processor; and (f) a memory control unit (12) connected to said main memory and including an address translation unit (75) for translating the virtual address to a physical address for controlling memory accesses from said processors, said address translating unit having status flags for allowing the address translation to be effected differently for the access from said file processor and the accesses from other processors.
Claim 2
Dependent Claim
181 words
1 . A virtual storage data processing system comprising: (a) a main memory (10) for storing programs and data; (b) an external memory (20) for storing programs and data to be stored in said main memory; (c) at least one job processor (40) for accessing said main memory with a virtual address to execute instructions; (d) a file processor (22) for accessing said main memory with a virtual address to transfer programs and data between said main memory and said external memory; (e) at least one cache memory (41, 42) located is said job processor for storing a partial copy of said main memory and accessing said main memory by a virtual memory by said job processor; and (f) a memory control unit (12) connected to said main memory and including an address translation unit (75) for translating the virtual address to a physical address for controlling memory accesses from said processors, said address translating unit having status flags for allowing the address translation to be effected differently for the access from said file processor and the accesses from other processors.
Claim 3
Dependent Claim
118 words
A virtual storage data processing system according to Claim 1 wherein said memory control unit includes: (a) a first register (71) for latching the virtual address transferred from said processor; (b) said address translation unit (75) for translating the virtual address latched in said first register to the physical address; and (c) a second register (72) for storing the physical address from said address translation unit, latching of the virtual address to said first register, address translation of the content of said first register and storing the translated physical address in said second register and initiation of said main memory by addressing said main memory by the content of said second register being sequentially and parallelly carried out.
Claim 4
Dependent Claim
66 words
A virtual storage data processing system according to Claim 1 further comprising: a common bus (50) for connecting said plurality of processors with said memory controller; said common bus being shared by said plurality of processors, each of said processors, when it accesses said main memory, using said common bus only in a transfer cycle of the virtual address and a receiving cycle of read data.
Claim 5
Dependent Claim
103 words
A virtual storage data processing system according to Claim 1 wherein said job processor includes: (a) an instruction cache (41) for storing instructions fetched from said main memory; (b) a data cache (42) for storing data read from said main memory; - (c) an instruction unit (43) connected to said instruction cache for fetching and decoding an instruction word to be executed next from said instruction cache; and (d) an execution unit (44) connected to said instruction unit and said data cache for reading necessary data from said data cache in accordance with an instruction from said instruction unit to execute the instruction.
Claim 6
Dependent Claim
118 words
A virtual storage data processing system according to Claim 1 wherein said cache memory includes: (a) a data unit (81-I, 81-D) for retaining a partial copy of said main memory; (b) a directory (82-I, 82-D) for retaining the virtual address or said main memory stored in said data unit; (c) a valid indication unit for indicating validity of said virtual address; (d) a latch register (43, 44) for latching the virtual address sent from said file processor; (e) compare means (160-I, 160-D) for comparing the virtual address latched in said latch register with the virtual address retained in said directory; and clear means (169-I, 169-D) for cleaning said valid indication unit in accordance with the result of comparison.
Claim 7
Dependent Claim
45 words
A virtual storage data processing system according to Claim 1 wherein said address translation unit includes means for determining whether a physical address corresponding to the virtual address is on the main memory or not and informing the result of determination to the requesting processor.
Claim 8
Dependent Claim
129 words
A virtual storage data processing system according to Claim 5 further comprising: a cache memory controller (162-1, 162-D) operable to refer to the content of said valid indication field and in a read access operation, to read a corresponding data block if it is in said cache memory and send it back to the requesting processor or sends the virtual address to said address translation unit if said data block is not in said cache memory, and in a write access operation, to write the corresponding data block in said cache if it is in said cache memory and write said corresponding data block in said main memory or if said corresponding data block is not in said cache memory, write said corresponding data block in said main memory.
Claim 9
Dependent Claim
72 words
A virtual storage data processing system according to Claim 7 wherein said cache memory controller, when a page fault occurs in the read access operation to said main memory, clears said valid indication field for the data block corresponding to the virtual address, and when the page fault occurs in the write access operation, clears the valid indication field for the corresponding data block if the latter is in said cache memory.
Claim 10
Dependent Claim
64 words
A virtual storage data processing system according to Claim 7 wherein said cache memory controller, when a cache miss occurs in the read access operation, issues a memory initiation signal to said main memory and sets a valid indication field for the corresponding data block, and when a page foult signal is received from said address translation unit, clears the corresponding valid indication field.
Claim 11
Dependent Claim
72 words
A virtual storage data processing system according to Claim 9 wherein said cache memory controller carries out setting of said valid indication field in the case of the read access to said main memory due to the cache miss and cleaning of said valid indication field in the case of the write access to said main memory from other processor, in the order of issuance of access requests onto said common bus.
References Cited (Backward Citations)
No citation records indexed.
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