Method and apparatus for reducing power consumption in digital electronic circuits

Claim 2

An integrated circuit with power conservation comprising: a plurality of functional blocks, each of which includes digital circuitry and at least one output control line, each of said functional blocks including a modulated clock input; and a power controller coupled to said at least one output control line of each of said functional blocks such that said power controller is responsive to a plurality of control lines, said power controller reducing power consumed by selected functional blocks in response to control signals on said plurality of control lines, wherein said power controller comprises a clock controller which provides a plurality of modulated clocks in response to said control signals on said plurality of control lines, wherein said clock controller is coupled to a modulated clock input of each of said functional blocks to provide a modulated clock for each of said functional blocks; wherein at least two of said functional blocks are coupled together as neighboring functional blocks, and wherein both of said neighboring functional blocks include a control line for itself and its neighbor to provide control signals to said clock controller.

Claim 3

An integrated circuit as recited in claim 1 wherein said functional blocks are coupled together for a flow of data between said functional blocks, and wherein each particular functional block includes N+1 control lines coupled to said clock controller, where N is the number of neighbor functional blocks of said particular functional block.

Claim 4

An integrated circuit as recited in claim 2 wherein a particular functional block can provide a control signal to said clock controller to shut off said particular functional block or a neighbor functional block.

Claim 5

An integrated circuit as recited in claim 1 wherein said clock controller has an input clock, wherein signals on said plurality of control lines are used to modulate said input clock to produce said modulated clocks.

Claim 6

An integrated circuit as recited in claim 4 wherein said clock controller further provides an output clock regular derived from said input clock, wherein there is a substantial, relative skew between said input clock and said output clock regular, but wherein there is little relative skew between said output clock regular and said modulated clocks.

Claim 9

A system with power conservation as recited in claim 6 wherein said modulated clocks are skewed with respect to said input clock.

Claim 10

A system with power conservation as recited in claim 7 further comprising an output regular clock which is skewed with respect to said input clock, but which is substantially in phase with said modulated clocks.

Claim 11

A system with power conservation as recited in claim 6 wherein one of said modulated clocks for a particular functional block has a frequency of about the same frequency as said input clock when said particular functional block is in operation, and has a frequency of about zero when said particular functional block is not in operation.

Claim 12

A system with power conservation as recited in claim 6 wherein a particular functional block can provide a signal to turn itself off or to turn off one or more of its neighbors.

Claim 13

A system with power conservation as recited in claim 6 wherein each of said functional blocks is provided data flow recognition circuitry which recognizes the direction of data flow, and with clock control line circuitry which provides signals on said clock control lines such that a neighbor functional block in the direction of data flow is active to process data.

Claim 14

A system with power conservation as recited in claim 11 wherein said clock control line circuitry further provides signals on said clock control lines such that a neighbor function block not in the direction of data flow is not active.

Claim 15

A system with power conservation as recited in claim 11 wherein said clock control circuitry further provides signals on said clock control lines such that one of said modulated clocks to said particular functional block causes said particular functional block to not be active.

Claim 16

A system with power conservation as recited in claim 6 wherein said clock controller includes: a main clock skew corrector receptive to said input clock and operative to produce an output clock regular; a plurality of combinational logic circuits, each receptive to clock control lines of a respective functional block and operative to develop a modulation signal for said respective functional block; and a plurality of clock gating logic circuits associated with respective ones of said plurality of combinational logic circuits, where each of said plurality of clock gating logic circuits is responsive to an associated modulation signal and to said output clock regular, and is operative to produce a plurality of modulated output clocks associated with respective ones of said plurality of functional blocks.

Claim 19

A method for reducing power consumption as recited in claim 15 wherein the deactivation of a particular functional block is accomplished by the step of reducing the frequency of a clock provided to said particular functional block.

Claim 20

A method for reducing power consumption as recited in claim 16 wherein said step of reducing the frequency of a clock is accomplished by modulating a regular clock with a modulation signal to provide a modulated clock such that a frequency of said modulated clock is either about the frequency of said regular clock or is about zero.

Claim 21

A method for reducing power consumption as recited in claim 15 further comprising the steps of: within each particular functional block, determining a direction of data flow; and creating modulated clocks for neighboring functional blocks of said particular functional blocks which controls their activation and deactivation.

Claim 22

A method for reducing power consumption as recited in claim 18 further comprising the steps of requesting the activation of a neighbor functional block that is in the direction of data flow, and requesting the deactivation of a neighbor functional block that is not in the direction of data flow.

Claim 23

An integrated circuit with power conservation comprising: a plurality of functional blocks, each of which includes digital circuitry and at least one output control line which carries control signals that pertains to potential power usage in said integrated circuit; and a power controller coupled to said at least one output control line of each of said functional blocks such that said power controller is responsive to said control signals on a plurality of control lines, said power controller reducing power consumed by selected functional blocks in response to said control signals.

Claim 24

An integrated circuit with power conservation comprising: a plurality of functional blocks, each of which includes digital circuitry and at least one output control line which carries control signals that pertains to potential power usage in said integrated circuit; and a power controller coupled to said at least one output control line of each of said functional blocks such that said power controller is responsive to said control signals on a plurality of control lines, said power controller reducing power consumed by selected functional blocks in response to said control signals.

Claim 25

An integrated circuit as recited in claim 20 wherein each of said functional blocks further includes a clock input, and wherein said power controller is a clock controller coupled to said clock input of each of said functional blocks, such that power can be reduced by reducing the frequency of a particular clock at a clock input of a particular functional block.

Claim 26

An integrated circuit as recited in claim 21 wherein said clock input of each of said functional blocks is a modulated clock input, and wherein said clock controller is operative to provide a plurality of modulated clocks, one each, to said functional blocks in response to said control signals on said plurality of control lines.

Claim 27

An integrated circuit as recited in claim 22 wherein said functional blocks are coupled together for a flow of data between said functional blocks, and wherein each particular functional block includes N+1 control lines coupled to said clock controller, where N is the number of neighbor functional blocks of said particular functional block.

Claim 28

An integrated circuit as recited in claim 23 wherein a particular functional block can provide a control signal to said clock controller to shut off said particular functional block or a neighbor functional block.

Claim 29

An integrated circuit as recited in claim 22 wherein said clock controller has an input clock, wherein signals on said plurality of control lines are used to modulate said input clock to produce said modulated clocks.

Claim 30

An integrated circuit as recited in claim 25 wherein said clock controller further provides an output clock regular derived from said input clock, wherein there is a substantial, relative skew between said input clock and said output clock regular, but wherein there is little relative skew between said output clock regular and said modulated clocks. .Iadd.

Claim 31

A system of circuits with power conservation, comprising: a plurality of functional blocks capable of processing data, each of the blocks including digital circuitry and at least one output control line that carries control signals pertaining to potential power usage; and a power controller coupled to each of the output control lines such that the power controller is responsive to the control signals on a plurality of control lines, the power controller being configured and arranged to reduce power consumed by selected functional blocks in response to the control signals..Iaddend..Iadd.28. A system of circuits with power conservation, according to claim 27, wherein the power controller is configured and arranged to reduce power consumed by selected functional blocks by modulating clock signals driving the selected functional blocks..Iaddend..Iadd.29. A system of circuits with power conservation, according to claim 27, wherein the power controller is configured and arranged to reduce power consumed by selected functional blocks by modulating operating power supplied to the selected functional blocks..Iaddend..Iadd.30. A system of circuits with power conservation, according to claim 27, wherein at least one of the plurality of functional blocks includes an external interface..Iaddend..Iadd.31. A system of circuits with power conservation, comprising: a plurality of functional blocks capable of processing data, each of the blocks including digital circuitry and at least one output control line that carries control signals pertaining to potential power usage; and a power controller coupled to each of the output control lines such that the power controller is responsive to the control signals on a plurality of control lines, the power controller being configured and arranged to reduce power consumed by selected functional blocks by modulating clock signals driving the selected functional blocks and by modulating operating power supplied to the selected functional blocks..Iaddend..Iadd.32. A system of circuits with power conservation, according to claim 27, wherein at least one of the plurality of functional blocks includes an external

Claim 32

interface..Iaddend..Iadd.33. A system of circuits with power conservation, comprising: a plurality of functional blocks capable of processing data, each of the blocks including digital circuitry and at least one output control line that carries control signals pertaining to potential power usage; and power consumption means for controlling power consumption, the power consumption means being coupled to each of the output control lines such that the power consumption means is responsive to the control signals on a plurality of control lines, the power consumption means and the functional blocks being configured and arranged to reduce power consumed by selected functional blocks by modulating clock signals driving the selected functional blocks and by modulating operating power supplied to the selected functional blocks..Iaddend..Iadd.34. A method for conserving power in a system having a plurality of functional blocks capable of processing data, each of the blocks including digital circuitry, the method comprising: from each of the functional blocks, generating control signals on at least one output control line, the control signals pertaining to potential power usage; and reducing power consumed by selected functional blocks in response to the control signals by modulating at least one clock signal driving the selected functional blocks..Iaddend..Iadd.35. A method, according to claim 34, further comprising reducing power consumed by selected functional blocks by modulating clock signals driving the selected functional blocks..Iaddend..Iadd.36. A method, according to claim 34, further comprising reducing power consumed by selected functional blocks by modulating operating power supplied to the selected functional blocks..Iaddend..Iadd.37. A method for conserving power in system having a plurality of functional blocks capable of processing data, each of the blocks including digital circuitry, the method comprising: from each of the functional blocks, generating control signals on at least one output control line, the control signals pertaining to potential power usage; and in response to the control signals, reducing power consumed by selected functional blocks by modulating clock signals driving the selected functional blocks and by modulating operating power supplied to the selected functional blocks..Iaddend.