EP0624837A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Electronic apparatus with reduced power consumption
Assignee: International Business Machines Corp
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Filing: 1994-04-15
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Granted: —
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Expires: 2014-04-15
Abstract
Abstract A method and circuitry are provided, in which a first operation is performed with first circuitry. A second operation is performed with second circuitry. A first signal is generated in response to the first operation. A second signal is generated in response to the second operation. Power consumption is adjusted within the second circuitry in response to the first and second signals.
Inventors
- 👤 Michael Clay Alexander
- 👤 Arturo Lopez Arizpe
- 👤 Gianfranco Gerosa
- 👤 James Allan Kahle
- 👤 Aubrey Deene Ogden
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 15:19
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/324; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
77 words
Electronic apparatus comprising: first digital circuitry for performing a first operation and generating a first signal in response thereto; second digital circuitry coupled to said first circuitry for performing a second operation and generating a second signal in response thereto; and third circuitry coupled to said first and second circuitry for adjusting power consumption within said second circuitry in response to said first and second signals by adjusting a frequency of clock transitions within said second circuitry.
Claim 2
Dependent Claim
40 words
Electronic apparatus as claimed in claim 1 wherein said third circuitry reduces said frequency in response to said second signal indicating said second operation awaits said first operation while said first signal indicates said first operation is not being performed.
Claim 3
Dependent Claim
19 words
Electronic apparatus as claimed in claim 1 or claim 2 wherein said third circuitry reduces said frequency to zero.
Claim 4
Dependent Claim
18 words
Electronic apparatus as claimed in any preceding claim wherein said third circuitry is integral with said second circuitry.
Claim 5
Dependent Claim
43 words
Electronic apparatus as claimed in any preceding claim wherein said first circuitry comprises: operation circuitry for performing said first operation; and detection circuitry coupled to said operation circuitry for detecting performance of said first operation and generating said first signal in response thereto.
Claim 6
Dependent Claim
53 words
Electronic apparatus as claimed in any preceding claim wherein the first circuitry comprises: an instruction dispatcher for dispatching an instruction and generating a first signal in response thereto; and the second circuitry comprises: an execution unit coupled to said instruction dispatcher for awaiting said instruction and generating a second signal in response thereto.
Claim 7
Dependent Claim
22 words
Electronic apparatus as claimed in claim 6 wherein said clock transitions are distributed to a plurality of latches within said execution unit.
Claim 8
Dependent Claim
13 words
Electronic apparatus as claimed in claim 7 wherein said latches are CMOS latches.
Claim 9
Dependent Claim
52 words
Electronic apparatus as claimed in any preceding claim wherein the first circuity comprises: a cache memory for outputting information and generating a first signal in response thereto; and the second circuity comprises: an input unit coupled to said cache memory for awaiting said information and generating a second signal in response thereto.
Claim 10
Dependent Claim
19 words
Electronic apparatus as claimed in claim 9 wherein said input unit is an instruction buffer/dispatch unit of a processor.
Claim 11
Dependent Claim
19 words
Electronic apparatus as claimed in claim 9 or claim 10 wherein said cache memory is an instruction cache memory.
Claim 12
Dependent Claim
30 words
An integrated circuit, comprising electronic apparatus as claimed in any preceding claim for adjusting power consumption within only a portion of the integrated circuit in response to said first signal.
Claim 13
Independent Claim
75 words
A method for operating electronic apparatus with reduced power consumption, comprising the steps of: performing a first operation with first circuitry; performing a second operation with second circuitry; generating a first signal in response to said first operation; generating a second signal in response to said second operation; and adjusting power consumption within said second circuitry in response to said first and second signals by adjusting a frequency of clock transitions within said second circuitry.
Claim 14
Dependent Claim
48 words
A method as claimed in Claim 13 wherein said step of adjusting said clock transitions comprises the step of reducing said frequency in response to said second signal indicating said second operation awaits said first operation while said first signal indicates said first operation is not being performed.
References Cited (Backward Citations)
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