Semiconductor memory

Claim 2

applied through said pair of switching elements..]. 4. A semiconductor memory according to claim 3, wherein said switching elements comprise a pair of transistors, each having an input terminal connected to a respective data line portion, an output terminal connected to said second differential amplifer, and a control terminal to which a control signal is

Claim 3

applied. .[.5. A semiconductor memory according to claim 1, wherein each of said memory cells comprises a metal-oxide-semiconductor transistor and a storage capacitor connected therewith..]. .[.6. A semiconductor memory according to claim 1, wherein, for each of said data line portions, the memory cells coupled thereto are coupled, alternately, to every other word line..]. .[.7. A semiconductor memory according to claim 1, wherein, for each of said data line portions, the memory cells coupled thereto are coupled in alternate pairs of adjacent word lines..]. .[.8. A semiconductor memory according to claim 1, wherein for each of said data line portions, the memory cells coupled thereto are coupled in alternate groups of four of adjacent word lines..]. .[.9. A semiconductor memory according to claim 1, wherein said memory cells are coupled to said data line portions and said word lines so that the electrical characteristics of said data line portions are balanced with respect to each other..]. .[.10. A semiconductor memory according to claim 1, wherein the number of memory cells connected to one of the data line portions of said pair of data line portions is equal to the number of memory cells connected to the other of the data line portions of said pair of data line portions..].

Claim 4

A semiconductor memory according to claim .[.3.]. .Iadd.2.Iaddend., further comprising a pair of second word lines orthogonally crossing over said data line portions; a first dummy memory cell coupled to one of the data line portions of said pair of data line portions and one of said second word lines at the cross point thereof; and a second dummy memory cell coupled to the other of the data line portions of said pair of data line portions and the other of said second word lines

Claim 5

at the cross point thereof. 12. A semiconductor memory according to claim 11, wherein said switching elements comprise a pair of transistors, each having an input terminal connected to a respective data line portion, an output terminal connected to said second differential amplifier, and a control terminal to which a control signal is applied. .[.13. A semiconductor memory according to claim 1, wherein said data line portions are formed of aluminum and said first word lines are formed of

Claim 6

polysilicon..]. 14. A random access semiconductor memory comprising: first and second data line portions disposed parallel and adjacent to each other.Iadd..Iaddend.; a plurality of first word lines orthgonally crossing over each of said data line portions; a plurality of memory cells, disposed at the cross points of said first word lines and one of said data line portions, each of which memory cells is capable of storing selected information to be written therein and is capable of reading out information stored therein, each memory cell having an address terminal connected to a respective word line so that each word line is connected to the address terminal of only one memory cell, and having a data terminal connected to one of said data line portions; a differential amplifier connected to each of said data line portions for differentially amplifying signals supplied thereby; means, connected to said differential amplifier and said data line portions; for deriving output signals representative of signals on said pair of data line portions; a pair of second word lines orthogonally crossing over each of said data line portions; a first dummy memory cell, disposed at the crosspoint of one of said second word lines and said first data line, and being capable of storing selected information to be written therein, and being capable of reading out information stored therein, and having an address terminal connected to said one of said second word lines, and having a data terminal connected to said first data line portion; and a second dummy memory cell, disposed at the crosspoint of the other of said second word lines and said second data line, and being capable of storing selected information to be written therein, and being capable of reading out information stored therein, and having an address terminal connected to said other of said second word lines, and having a data terminal connected to said second data line portion.Iadd., wherein driving signals are applied to one of said first word lines and one of said second word lines, at the same time, so that data from one of said plurality of memory cells and one of said dummy memory cells are, respectively read out on one and the other of said data line portions, at the same time. .Iaddend.

Claim 7

polysilicon..]. 14. A random access semiconductor memory comprising: first and second data line portions disposed parallel and adjacent to each other.Iadd..Iaddend.; a plurality of first word lines orthgonally crossing over each of said data line portions; a plurality of memory cells, disposed at the cross points of said first word lines and one of said data line portions, each of which memory cells is capable of storing selected information to be written therein and is capable of reading out information stored therein, each memory cell having an address terminal connected to a respective word line so that each word line is connected to the address terminal of only one memory cell, and having a data terminal connected to one of said data line portions; a differential amplifier connected to each of said data line portions for differentially amplifying signals supplied thereby; means, connected to said differential amplifier and said data line portions; for deriving output signals representative of signals on said pair of data line portions; a pair of second word lines orthogonally crossing over each of said data line portions; a first dummy memory cell, disposed at the crosspoint of one of said second word lines and said first data line, and being capable of storing selected information to be written therein, and being capable of reading out information stored therein, and having an address terminal connected to said one of said second word lines, and having a data terminal connected to said first data line portion; and a second dummy memory cell, disposed at the crosspoint of the other of said second word lines and said second data line, and being capable of storing selected information to be written therein, and being capable of reading out information stored therein, and having an address terminal connected to said other of said second word lines, and having a data terminal connected to said second data line portion.Iadd., wherein driving signals are applied to one of said first word lines and one of said second word lines, at the same time, so that data from one of said plurality of memory cells and one of said dummy memory cells are, respectively read out on one and the other of said data line portions, at the same time. .Iaddend.

Claim 8

.[. . A random access semiconductor memory according to claim 14, wherein said output signal deriving means comprises a pair of switching elements connected to said data line portions and a second differential amplifier connected to said pair of switching elements, to which the signals on said data line portions are selectively

Claim 9

applied through said pair of switching elements..]. 16. A semiconductor memory according to claim 15, wherein each of said memory cells comprises a metal-oxide-semiconductor transistor and a storage capacitor connected

Claim 10

therewith. 17. A semiconductor memory according to claim 16, wherein said switching elements comprise a pair of transistors, each having an input terminal connected to a respective data line portion, an output terminal connected to said second differential amplifier, and a control terminal to

Claim 11

which a control signal is applied. .Iadd.18. A semiconductor memory comprising: at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data; a first differential amplifier to which signals on said pair of data line portions are respectively applied; means, connected to said first differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions and said output signal deriving means having: a pair of switching elements connected to said data line portions; and a second differential amplifier connected to said pair of switching elements, to which the signals on said data line portions are selectively

Claim 12

which a control signal is applied. .Iadd.18. A semiconductor memory comprising: at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data; a first differential amplifier to which signals on said pair of data line portions are respectively applied; means, connected to said first differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions and said output signal deriving means having: a pair of switching elements connected to said data line portions; and a second differential amplifier connected to said pair of switching elements, to which the signals on said data line portions are selectively

Claim 13

applied through said pair of switching elements. .Iaddend. .Iadd.19. A semiconductor memory comprising: at least a pair of data line portions formed of aluminum arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines formed of polysilicon orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data; a differential amplifier to which signals on said pair of data line portions are respectively applied; and means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions. .Iaddend. .Iadd.20. A semiconductor memory comprising: at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data, said memory cells coupled such that pairs of cells coupled to adjacent word lines are alternately coupled to one and the other of said pair of data lines; a differential amplifier to which signals on said pair of data line portions are respectively applied; and means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions. .Iaddend. .Iadd.21. A semiconductor memory comprising: at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data, the memory cells of said data line portions, said memory cells coupled such that groups of four cells coupled to four adjacent word lines are alternately coupled to one and the other of said pair of data lines; a differential amplifier to which signals on said pair of data line portions are respectively applied; and means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said

Claim 14

applied through said pair of switching elements. .Iaddend. .Iadd.19. A semiconductor memory comprising: at least a pair of data line portions formed of aluminum arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines formed of polysilicon orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data; a differential amplifier to which signals on said pair of data line portions are respectively applied; and means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions. .Iaddend. .Iadd.20. A semiconductor memory comprising: at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data, said memory cells coupled such that pairs of cells coupled to adjacent word lines are alternately coupled to one and the other of said pair of data lines; a differential amplifier to which signals on said pair of data line portions are respectively applied; and means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions. .Iaddend. .Iadd.21. A semiconductor memory comprising: at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data, the memory cells of said data line portions, said memory cells coupled such that groups of four cells coupled to four adjacent word lines are alternately coupled to one and the other of said pair of data lines; a differential amplifier to which signals on said pair of data line portions are respectively applied; and means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said

Claim 15

pair of data line portions. .Iaddend. .Iadd.22. A semiconductor memory comprising: at least two pairs of data line portions arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data; first and second differential amplifiers to which signals on said two pairs of data line portions are respectively applied, one of said differential amplifiers connected to one side of an arrangement formed by said data line portions and the other differential amplifier connected to the other side thereof; and means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions. .Iaddend. .Iadd.23. A semiconductor memory comprising: at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data, the memory cells of said data line portions, said memory cells coupled such that pairs of cells coupled to adjacent word lines are alternately coupled to one and the other of said pair of data lines; a differential amplifier to which signals on said pair of data line portions are respectively applied; and each of said memory cells being a metal-oxide semiconductor transistor having an input electrode, an output electrode and a gate electrode, the respective output electrodes of two MOS transistors in two adjacent memory cells being connected at the same location to one data line portion and the respective gate electrodes thereof being connected to two respective adjacent word lines. .Iaddend. .Iadd.24. A semiconductor memory comprising: at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data; a differential amplifier to which signals on said pair of data line portions are respectively applied; means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions; and each of said memory cells comprising a metal-oxide semiconductor transistor with source drain and gate regions, the direction of the channel formed between the source and drain regions of said MOS transistor being parallel

Claim 16

pair of data line portions. .Iaddend. .Iadd.22. A semiconductor memory comprising: at least two pairs of data line portions arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data; first and second differential amplifiers to which signals on said two pairs of data line portions are respectively applied, one of said differential amplifiers connected to one side of an arrangement formed by said data line portions and the other differential amplifier connected to the other side thereof; and means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions. .Iaddend. .Iadd.23. A semiconductor memory comprising: at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data, the memory cells of said data line portions, said memory cells coupled such that pairs of cells coupled to adjacent word lines are alternately coupled to one and the other of said pair of data lines; a differential amplifier to which signals on said pair of data line portions are respectively applied; and each of said memory cells being a metal-oxide semiconductor transistor having an input electrode, an output electrode and a gate electrode, the respective output electrodes of two MOS transistors in two adjacent memory cells being connected at the same location to one data line portion and the respective gate electrodes thereof being connected to two respective adjacent word lines. .Iaddend. .Iadd.24. A semiconductor memory comprising: at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data; a differential amplifier to which signals on said pair of data line portions are respectively applied; means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions; and each of said memory cells comprising a metal-oxide semiconductor transistor with source drain and gate regions, the direction of the channel formed between the source and drain regions of said MOS transistor being parallel

Claim 17

to the direction of said data line portions. .Iaddend. .Iadd.25. A semiconductor memory comprising: at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data; a differential amplifier to which signals on said pair of data line portions are respectively applied; means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions; and each of said memory cells comprising a metal-oxide-semiconductor transistor having a gate electrode with the gate electrode of said MOS transistor in each memory cell formed by a portion of one of said first word lines. .Iaddend. .Iadd.26. A semiconductor memory comprising: at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines orthogonally crossing over said data line portions; a multiplicity of memory cells, formed at said surface, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data; a differential amplifier to which signals on said pair of data line portions are respectively applied; means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions; said output signal deriving means comprising a pair of switching elements connected to said data line portions and a pair of common data lines

Claim 18

to the direction of said data line portions. .Iaddend. .Iadd.25. A semiconductor memory comprising: at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data; a differential amplifier to which signals on said pair of data line portions are respectively applied; means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions; and each of said memory cells comprising a metal-oxide-semiconductor transistor having a gate electrode with the gate electrode of said MOS transistor in each memory cell formed by a portion of one of said first word lines. .Iaddend. .Iadd.26. A semiconductor memory comprising: at least a pair of data line portions arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines orthogonally crossing over said data line portions; a multiplicity of memory cells, formed at said surface, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data; a differential amplifier to which signals on said pair of data line portions are respectively applied; means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said pair of data line portions; said output signal deriving means comprising a pair of switching elements connected to said data line portions and a pair of common data lines

Claim 19

connected to said pair of switching elements. .Iaddend. .Iadd.27. A random access semiconductor memory comprising: first and second data line portions disposed parallel and adjacent to each other; a pluraltiy of first word lines orthogonally crossing over each of said data line portions; a plurality of memory cells, disposed at the cross points of said first word lines and one of said data line portions, each of which memory cells is capable of storing selected information to be written therein and is capable of reading out information stored therein, each memory cell having an address terminal connected to a respective word line so that each word line is connected to the address terminal of only one memory cell, and having a data terminal connected to one of said data line portions; a differential amplifier connected to each of said data line portions for differentially amplifying signals supplied thereby; means, connected to said differential amplifier and said data line portions for deriving output signals representative of signals on said pair of data line portions comprising: a pair of switching elements connected to said data line portions, and a second differential amplifier connected to said pair of switching elements, to which the signals on said data line portions are selectively amplified though said pair of switching elements; pair of second word lines orthogonally crossing over each of said data line portions; a first dummy memory cell, disposed at the crosspoint of one of said second word lines and said first data line, and being capable of storing selected information to be written therein, and being capable of reading out information stored therein and having an address terminal connected to said one of said second word lines, and having a data terminal connected to said first data line portion; and a second dummy memory cell, disposed at the crosspoint of the other of said second word lines and said second data line, and being capable of storing selected information to be written therein, and being capable of reading out information stored therein, and having an address terminal connected to said other of said second word lines, and having a data terminal

Claim 20

connected to said pair of switching elements. .Iaddend. .Iadd.27. A random access semiconductor memory comprising: first and second data line portions disposed parallel and adjacent to each other; a pluraltiy of first word lines orthogonally crossing over each of said data line portions; a plurality of memory cells, disposed at the cross points of said first word lines and one of said data line portions, each of which memory cells is capable of storing selected information to be written therein and is capable of reading out information stored therein, each memory cell having an address terminal connected to a respective word line so that each word line is connected to the address terminal of only one memory cell, and having a data terminal connected to one of said data line portions; a differential amplifier connected to each of said data line portions for differentially amplifying signals supplied thereby; means, connected to said differential amplifier and said data line portions for deriving output signals representative of signals on said pair of data line portions comprising: a pair of switching elements connected to said data line portions, and a second differential amplifier connected to said pair of switching elements, to which the signals on said data line portions are selectively amplified though said pair of switching elements; pair of second word lines orthogonally crossing over each of said data line portions; a first dummy memory cell, disposed at the crosspoint of one of said second word lines and said first data line, and being capable of storing selected information to be written therein, and being capable of reading out information stored therein and having an address terminal connected to said one of said second word lines, and having a data terminal connected to said first data line portion; and a second dummy memory cell, disposed at the crosspoint of the other of said second word lines and said second data line, and being capable of storing selected information to be written therein, and being capable of reading out information stored therein, and having an address terminal connected to said other of said second word lines, and having a data terminal

Claim 21

connected to said second data line portion. .Iaddend. .Iadd.28. A semiconductor memory comprising: at least a pair of data line portions formed of aluminum arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines formed of polysilicon orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data for each of said data line portions, said memory cells coupled such that pairs of cells coupled to adjacent word lines are alternately coupled to one and the other of said pair of data lines; a differential amplifier to which signals on said pair of data line portions are respectively applied; means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said

Claim 22

connected to said second data line portion. .Iaddend. .Iadd.28. A semiconductor memory comprising: at least a pair of data line portions formed of aluminum arranged in parallel with each other and at positions adjacent to each other; a plurality of first word lines formed of polysilicon orthogonally crossing over said data line portions; a multiplicity of memory cells, each of which is coupled to a respective data line portion and a respective first word line at the cross point thereof and can perform random access for write-in and read-out of data for each of said data line portions, said memory cells coupled such that pairs of cells coupled to adjacent word lines are alternately coupled to one and the other of said pair of data lines; a differential amplifier to which signals on said pair of data line portions are respectively applied; means, connected to said differential amplifier and said data line portions, for deriving output signals representative of signals on said

Claim 23

pair of data line portions. .Iaddend. .Iadd.29. A semiconductor memory according to claim 22, wherein said differential amplifiers are arranged alternately on one side and the other side of the arrangement formed by said pairs of data line portions. .Iaddend. .Iadd.30. A semiconductor memory according to claim 24, wherein said data line portion overlaps said

Claim 24

channel as viewed in the vertical direction. .Iaddend. .Iadd.31. A semiconductor memory according to claim 1, wherein said pair of second word lines are arranged at positions adjacent to each other. .Iaddend. .Iadd.32. A semiconductor memory according to claim 18, wherein, for each of said data line portions, the memory cells coupled thereto are coupled in alternate pairs of adjacent word lines. .Iaddend. .Iadd.33. A semiconductor memory according to claim 18, wherein said data line portions are formed of aluminum and said first word lines are formed of

Claim 25

polysilicon. .Iaddend. .Iadd.34. A semiconductor memory according to claim 20, wherein each of said memory cells comprises a metal-oxide-semiconductor transistor, the respective output electrodes of two MOS transistors in two adjacent memory cells are connected at the same location to one data line portion, and the respective gate electrodes thereof are connected to two respective adjacent first word lines. .Iaddend. .Iadd.35. A semiconductor memory according to claim 34, wherein the direction of the channel formed between the source and drain regions of said MOS transistor is parallel to the direction of said data line portion. .Iaddend. .Iadd.36. A semiconductor memory according to claim 35, wherein said data line portion overlaps said channel as viewed in the vertical direction. .Iaddend. .Iadd.37. A semiconductor memory according to claim 34, wherein the gate electrode of said MOS transistor in each memory cell is formed by a portion of said first word line. .Iaddend. .Iadd.38. A semiconductor memory according to claim 34, further comprising a pair of second word lines orthogonally crossing over said data line portions and being arranged at positions adjacent to each other; a first dummy memory cell coupled to one of the data line portions and one of said second word lines at the cross point thereof; and a second dummy memory cell coupled to the other of the data line portions of said pair of data line portions and the other of said second word lines

Claim 26

at the cross point thereof. .Iaddend. .Iadd.39. A semiconductor memory according to claim 19, wherein said output signal deriving means comprises a pair of switching elements connected to said data line portions and a second differential amplifier connected to said pair of switching elements, to which the signals on said data line portions are selectively applied through said pair of switching elements, and the memory cells coupled to said data line portions are coupled in alternate pairs of adjacent word lines for each of said data line portions. .Iaddend. .Iadd.40. A semiconductor memory according to claim 19, wherein each of said memory cells is formed at a surface portion of a semiconductor body having one conductivity type and has a semiconductor region being formed in said surface portion and having the opposite conductivity type to said semiconductor body, said first word lines are formed on an insulator disposed on said body, and each of said data line portions has a first portion thereof being contact with said semiconductor region, and a second portion thereof insulated from both said body and said first word lines. .Iaddend. .Iadd.41. A semiconductor memory according to claim 26, wherein said output signal deriving means further comprises another differential amplifier connected to said pair of data lines, to which the signals on said data line portions are selectively applied through said pair of

Claim 27

switching elements. .Iaddend. .Iadd.42. A semiconductor memory according to claim 26, wherein each of said switching elements comprises a MOS transistor having source and drain regions, and each of said pair of data line portions is connected through the channel formed between the source and drain regions of said transistor to each of said pair of data lines. .Iaddend.