US8421197B2
Active / In Force
US
⏱️ 4.3 years remaining
Integrated circuit package system with warp-free chip
Assignee: Stats Chippac Pte Ltd
•
Filing: 2011-02-08
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Granted: 2013-04-16
•
Expires: 2031-02-08
Abstract
Abstract An integrated circuit package system includes: a semiconductor chip; a stress-relieving layer on the semiconductor chip; an adhesion layer on the stress relieving layer; and electrical interconnects bonded to the adhesion layer.
Inventors
- 👤 Byung Tai Do
- 👤 Il Kwon Shim
- 👤 Antonio B. Dimaano, Jr.
- 👤 Heap Hoe Kuan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:40
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/40; H10W70/411; H10W70/415; H10P; H10P72/00; H10P72/70; H10P72/74; H10W70/417; H10W70/421; H10W70/424; H10W74/00; H10W74/01; H10W74/019; H10W74/10; H10W74/111; H10W72/00; H10W72/01; H10W72/013; H10W72/01331; H10W72/01336; H10W72/071; H10W72/073; H10W72/07331; H10W72/07337; H10W72/07338; H10W72/075; H10W72/30; H10W72/351; H10W72/353; H10W72/354; H10W72/381; H10W72/851; H10W72/874; H10W72/884; H10W90/00; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
46 words
An integrated circuit package system comprising: a semiconductor chip; a stress-relieving layer on the semiconductor chip; an adhesion layer on the stress relieving layer; electrical interconnects bonded to the adhesion layer; and an additional stress-relieving layer on the adhesion layer and attached between the electrical interconnects.
Claim 2
Dependent Claim
46 words
An integrated circuit package system comprising: a semiconductor chip; a stress-relieving layer on the semiconductor chip; an adhesion layer on the stress relieving layer; electrical interconnects bonded to the adhesion layer; and an additional stress-relieving layer on the adhesion layer and attached between the electrical interconnects.
Claim 3
Dependent Claim
41 words
The system as claimed in claim 1 wherein: the adhesion layer is on selected regions of the stress-relieving layer adjacent the diced sides of the semiconductor chip; and the semiconductor chip is mounted by the adhesion layer on the electrical interconnects.
Claim 4
Dependent Claim
30 words
The system as claimed in claim 1 wherein: the adhesion layer is thicker than the stress-relieving layer; and the adhesion layer on the electrical interconnects and over the sides thereof.
Claim 5
Dependent Claim
20 words
The system as claimed in claim 1 wherein: the additional stress-relieving layer holds the semiconductor chip over the electrical interconnects.
Claim 6
Dependent Claim
34 words
The system as claimed in claim 1 further comprising: bond wires electrically connecting the semiconductor chip to the electrical interconnects; and an encapsulant encapsulating the semiconductor chip, the bond wires, and the electrical interconnects.
Claim 7
Dependent Claim
46 words
The system as claimed in claim 1 wherein: the stress-relieving layer is a low modulus stress-relieving layer; the adhesion layer is a high modulus adhesion layer; the low modulus stress-relieving layer and the high modulus adhesion layer are fully cured; and the electrical interconnects are leadfingers.
Claim 8
Dependent Claim
46 words
The system as claimed in claim 6 wherein: the high modulus adhesion layer is on selected regions of the low modulus stress-relieving layer adjacent the diced sides of the semiconductor chip; and the semiconductor chip is mounted by the high modulus adhesion layer on the leadfingers.
Claim 9
Dependent Claim
35 words
The system as claimed in claim 6 wherein: the high modulus adhesion layer is thicker than the low modulus stress-relieving layer; and the high modulus adhesion layer on the leadfingers and over the sides thereof.
Claim 10
Dependent Claim
19 words
The system as claimed in claim 6 wherein: the additional stress-relieving layer holds the semiconductor chip on the leadfingers.
Claim 11
Dependent Claim
32 words
The system as claimed in claim 6 further comprising: bond wires electrically connecting the semiconductor chip to the leadfingers; and an encapsulant encapsulating the semiconductor chip, the bond wires, and the leadfingers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2016-04-15 | 2016-10-15 | 2017-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2020-04-15 | 2020-10-15 | 2021-04-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2024-04-15 | 2024-10-15 | 2025-04-16 | $7700.00 | Window Closed / Lapsed |