US6359221B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Resin sealed semiconductor device, circuit member for use therein
Assignee: Dai Nippon Printing Co Ltd
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Filing: 1998-07-29
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Granted: 2002-03-19
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Expires: 2018-07-29
Abstract
Abstract There is disclosed a resin-sealed semiconductor device in which plural circuit portions integrally having inner and outer terminals are arranged two-dimensionally substantially in a plane and electrically independent of one another, and have leads for integrally interconnecting the inner and outer terminals, surfaces of the circuit portions are semiconductor element mounted faces with the inner and outer terminals and the leads forming one plane, the inner terminals and the leads are thinner than the outer terminals, back surfaces of the circuit portions are provided with terminal faces of the inner and outer terminals, a terminal mounted face of the semiconductor element is mounted via an insulating layer onto the semiconductor element mounted faces of the circuit portions, and the semiconductor element terminals are electrically connected with wires to the terminal faces of the inner terminal, and the whole is sealed with a resin in such a manner that the outer terminals are partially exposed to the outside. An occupation ratio of the semiconductor element in the semiconductor device is enhanced, the semiconductor device can be miniaturized, and a mounting density onto a circuit board can be enhanced. By forming outer electrodes on the outer terminals, multiple pins can further be provided, which is difficult with a small-sized semiconductor device such as conventional TSOP and the like.
Inventors
- 👤 Syuichi Yamada
- 👤 Makoto Nakamura
- 👤 Takayuki Takeshita
- 👤 Hiroshi Yagi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:12
CPC Classifications
H; H10; H10P; H10P72/00; H10P72/70; H10P72/74; H10W; H10W70/00; H10W70/01; H10W70/04; H10W70/042; H10W70/40; H10W70/411; H10W70/415; H10W70/421; H10W70/424; H10W72/00; H10W72/30; H10W74/00; H10W74/10; H10W74/111; H10W74/129; H10P72/7438; H10W72/071; H10W72/073; H10W72/07331; H10W72/07337; H10W72/07351; H10W72/07352; H10W72/075; H10W72/321; H10W72/381; H10W72/851; H10W72/853; H10W72/865; H10W72/874; H10W72/884; H10W72/90; H10W72/951; H10W72/952; H10W90/00; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49155; Y10T29/49158; Y10T29/49169; Y10T29/49171; Y10T29/49172
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
209 words
A resin-sealed semiconductor device, comprising: a semiconductor element having a top surface and a bottom surface with terminals formed on said top surface; and plural circuit portions having top surfaces and bottom surfaces with said top surfaces facing said bottom surface of said semiconductor element, wherein said plural circuit portions include, integrally formed inner terminals and outer terminals arranged two-dimensionally along a plane and electrically independent of one another, said top surfaces of said inner terminals of said circuit portions are electrically connected to said terminals of said semiconductor element with wires, said device is completely sealed with a resin in such a manner that said bottom surfaces of said outer terminals are partially exposed, said circuit portions have leads for integrally interconnecting said inner terminals and said outer terminals, said inner terminals and said leads are thinner than said outer terminals, said semiconductor element is mounted on said top surfaces of said circuit portions with an insulating layer disposed therebetween, wherein said device is configured as a chip size package (CSP) having a chip on lead (COL) structure, and wherein said outer terminals, said leads and a portion of said inner terminals of the circuit portions are directly underneath the semiconductor element with the insulating layer disposed therebetween.
Claim 2
Dependent Claim
209 words
A resin-sealed semiconductor device, comprising: a semiconductor element having a top surface and a bottom surface with terminals formed on said top surface; and plural circuit portions having top surfaces and bottom surfaces with said top surfaces facing said bottom surface of said semiconductor element, wherein said plural circuit portions include, integrally formed inner terminals and outer terminals arranged two-dimensionally along a plane and electrically independent of one another, said top surfaces of said inner terminals of said circuit portions are electrically connected to said terminals of said semiconductor element with wires, said device is completely sealed with a resin in such a manner that said bottom surfaces of said outer terminals are partially exposed, said circuit portions have leads for integrally interconnecting said inner terminals and said outer terminals, said inner terminals and said leads are thinner than said outer terminals, said semiconductor element is mounted on said top surfaces of said circuit portions with an insulating layer disposed therebetween, wherein said device is configured as a chip size package (CSP) having a chip on lead (COL) structure, and wherein said outer terminals, said leads and a portion of said inner terminals of the circuit portions are directly underneath the semiconductor element with the insulating layer disposed therebetween.
Claim 3
Dependent Claim
26 words
The device of claim 1 , wherein said bottom surfaces of said outer terminals which are partially exposed are provided with outer electrodes comprising solder balls.
Claim 4
Dependent Claim
16 words
The device of claim 2 , wherein said device is configured as a ball grid array(BGA).
Claim 5
Dependent Claim
16 words
The device of claim 1 , wherein said top surfaces of said inner terminals are flat.
Claim 6
Dependent Claim
44 words
The device of claim 1 , wherein said terminals of said semiconductor element are arranged on a periphery thereof on said top surface of said semiconductor element, and said inner terminals are arranged so as to correspond with respective terminals of said semiconductor element.
Claim 7
Dependent Claim
32 words
The device of claim 1 , wherein a metallic layer is provided between said top surfaces of said inner terminals and said wires electrically connected to said terminals of said semiconductor element.
Claim 8
Dependent Claim
23 words
The device of claim 6 , wherein said metallic layer comprises a layer of one of silver plating, gold plating and palladium plating.
Claim 9
Dependent Claim
35 words
The device of claim 1 , wherein each of said circuit portions is integrally provided with a semiconductor mounting lead on said outer terminal, and said semiconductor mounting lead is thinner than said outer terminal.
Claim 10
Dependent Claim
255 words
A circuit member used for manufacturing a resin-sealed semiconductor device configured as a chip size package (CSP) having a chip on lead (COL) structure, comprising: a removable outer frame member; and plural circuit portions extending from said outer frame member and independent of one another and adapted to accommodate a semiconductor element having a top surface and a bottom surface with terminals formed on said top surface, wherein said plural circuit portions have top surfaces and bottom surfaces with said top surfaces adapted to face said bottom surface of said semiconductor element, said plural circuit portions include, integrally formed inner terminals and outer terminals arranged two-dimensionally along a plane and electrically independent of one another, said top surfaces of said inner terminals of said circuit portions are adapted to be electrically connected to said terminals of said semiconductor element with wires, said circuit member except for said removable outer frame is adapted to be completely sealed with a resin in such a manner that said bottom surfaces of said outer terminals are partially exposed, said circuit portions have leads for integrally interconnecting said inner terminals and said outer terminals, said inner terminals and said leads are thinner than said outer terminals, said circuit member is adapted for mounting said semiconductor element on said top surfaces of said circuit portions with an insulating layer disposed therebetween, and wherein said outer terminals, said leads and a portion of said inner terminals of the circuit portions are directly underneath the semiconductor element with the insulating layer disposed therebetween.
Claim 11
Dependent Claim
255 words
A circuit member used for manufacturing a resin-sealed semiconductor device configured as a chip size package (CSP) having a chip on lead (COL) structure, comprising: a removable outer frame member; and plural circuit portions extending from said outer frame member and independent of one another and adapted to accommodate a semiconductor element having a top surface and a bottom surface with terminals formed on said top surface, wherein said plural circuit portions have top surfaces and bottom surfaces with said top surfaces adapted to face said bottom surface of said semiconductor element, said plural circuit portions include, integrally formed inner terminals and outer terminals arranged two-dimensionally along a plane and electrically independent of one another, said top surfaces of said inner terminals of said circuit portions are adapted to be electrically connected to said terminals of said semiconductor element with wires, said circuit member except for said removable outer frame is adapted to be completely sealed with a resin in such a manner that said bottom surfaces of said outer terminals are partially exposed, said circuit portions have leads for integrally interconnecting said inner terminals and said outer terminals, said inner terminals and said leads are thinner than said outer terminals, said circuit member is adapted for mounting said semiconductor element on said top surfaces of said circuit portions with an insulating layer disposed therebetween, and wherein said outer terminals, said leads and a portion of said inner terminals of the circuit portions are directly underneath the semiconductor element with the insulating layer disposed therebetween.
Claim 12
Dependent Claim
33 words
The circuit member of claim 9 , wherein when said bottom surfaces of said outer terminals are partially exposed, said circuit member is adapted to be provided with outer electrodes comprising solder balls.
Claim 13
Dependent Claim
20 words
The circuit member of claim 10 , wherein said circuit member is configured to accommodate a ball grid array (BGA).
Claim 14
Dependent Claim
17 words
The circuit member of claim 9 , wherein said top surfaces of said inner terminals are flat.
Claim 15
Dependent Claim
45 words
The circuit member of claim 9 , wherein when said terminals of said semiconductor element are arranged on a periphery thereof on said top surface of said semiconductor element, said inner terminals are arranged so as to correspond with respective terminals of said semiconductor element.
Claim 16
Dependent Claim
24 words
The circuit member of claim 9 , wherein a metallic layer is provided between said top surfaces of said inner terminals and said wires.
Claim 17
Dependent Claim
24 words
The circuit member of claim 14 , wherein said metallic layer comprises a layer of one of silver plating, gold plating and palladium plating.
Claim 18
Dependent Claim
36 words
The circuit member of claim 9 , wherein each of said circuit portions is integrally provided with a semiconductor mounting lead on said outer terminal, and said semiconductor mounting lead is thinner than said outer terminal.
References Cited (Backward Citations)
US4380042A
Cited
US5717252A
Cited
US5669774A
Cited
US5703407A
Cited
US5756380A
Cited
US5994773A
Cited
US5863805A
Cited
US6011694A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-03-18 | 2005-09-17 | 2006-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-03-18 | 2009-09-17 | 2010-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-03-18 | 2013-09-17 | 2014-03-19 | $7700.00 | Window Closed / Lapsed |