CMOS amplifiers with frequency compensating capacitors

Claim 2

A CMOS amplifier circuit, comprising: a differential input circuit including differentially coupled first NMOS input transistor having first gate, drain, and source terminals and second NMOS input transistor having second gate, drain, and source terminals; a first voltage reference node; a current mirror circuit including a third PMOS load transistor having third gate, drain, and source terminals, a fourth PMOS load transistor having fourth gate, drain, and source terminals, the third and fourth gate terminals coupled to the first and third drain terminals, the third and fourth source terminals coupled to the first voltage reference node, the fourth drain terminal coupled to the second drain terminal; an output stage circuit including an amplifier circuit having a gain, the amplifier circuit coupled between the second drain terminal and a signal output; a first compensating capacitor coupled between the second drain terminal and the first gate terminal; and a second compensating capacitor coupled between the signal output and the second gate terminal.

Claim 3

The CMOS amplifier circuit of claim 1 , wherein the first and second NMOS input transistors are approximately matched transistors each having a gate-to-drain capacitance approximately equal to a matched capacitance, and wherein the first and second compensating capacitors each have a capacitance approximately equal to the matched capacitance.

Claim 4

A CMOS amplifier circuit, comprising: a differential input circuit including differentially coupled first NMOS input transistor having first gate, drain, and source terminals and second NMOS input transistor having second gate, drain, and source terminals; a first voltage reference node; a current mirror circuit coupled to the first drain terminal, the second drain terminal, and the first voltage reference node; an output stage circuit coupled to the differential input circuit and the current mirror circuit, the output stage circuit including a signal output; a first compensating capacitor coupled between the second drain terminal and the first gate terminal; and a second compensating capacitor coupled between the signal output and the second gate terminal, wherein the first and second NMOS input transistors are approximately matched transistors each having a gate-to-drain capacitance approximately equal to a matched capacitance, and wherein the first and second compensating capacitors each have a capacitance approximately equal to the matched capacitance, wherein the output stage circuit comprises an amplifier circuit including a third PMOS output transistor having third gate, drain, and source terminals, the third gate terminal coupled to the second drain terminal, the third drain terminal coupled to the signal output.

Claim 5

A CMOS amplifier circuit, comprising: a differential input circuit including differentially coupled first NMOS input transistor having first gate, drain, and source terminals and second NMOS input transistor having second gate, drain, and source terminals; a first voltage reference node; a current mirror circuit coupled to the first drain terminal, the second drain terminal, and the first voltage reference node; an output stage circuit coupled to the differential input circuit and the current mirror circuit, the output stage circuit including a signal output; a first compensating capacitor coupled between the second drain terminal and the first gate terminal; and a second compensating capacitor coupled between the signal output and the second gate terminal, wherein the first and second NMOS input transistors are approximately matched transistors each having a gate-to-drain capacitance approximately equal to a matched capacitance, and wherein the first and second compensating capacitors each have a capacitance approximately equal to the matched capacitance, wherein the output stage circuit comprises an amplifier circuit including a third PMOS output transistor having third gate, drain, and source terminals, the third gate terminal coupled to the second drain terminal, the third drain terminal coupled to the signal output.

Claim 6

The CMOS amplifier circuit of claim 3 , wherein the current mirror circuit comprises a fourth PMOS load transistor having fourth gate, drain, and source terminals, a fifth PMOS load transistor having fifth gate, drain, and source terminals, the fourth and fifth gate terminals coupled to the first and fourth drain terminals, the fourth and fifth source terminals coupled to the first voltage reference node, the fifth drain terminal coupled to the second drain terminal.

Claim 7

The CMOS amplifier circuit of claim 4 , wherein the third source terminal is coupled to the first voltage reference node.

Claim 8

The CMOS amplifier circuit of claim 4 , comprising a source node coupled to the first source terminal and the second source terminal, a second voltage reference node, and a bias resistor coupled between the source node and the second voltage reference node.

Claim 9

The CMOS amplifier circuit of claim 3 , wherein the output stage circuit comprises an amplifier circuit having a gain.

Claim 10

The CMOS amplifier circuit of claim 1 , wherein the first NMOS input transistor has a first gate-to-drain capacitance, and the first compensating capacitor has a first compensation capacitance approximately equal to the first gate-to-drain capacitance.

Claim 11

The CMOS amplifier circuit of claim 8 , wherein the second NMOS input transistor has a second gate-to-drain capacitance, and the second compensating capacitor has a second compensation capacitance approximately equal to the second gate-to-drain capacitance divided by the gain of the output stage circuit.

Claim 12

The CMOS amplifier circuit of claim 9 , wherein the output stage circuit is configured for a gain of approximately one.

Claim 13

The CMOS amplifier circuit of claim 10 , wherein the first and second NMOS input transistors are approximately matched transistors, and the first and second gate-to-drain capacitances are approximately equal.

Claim 14

The CMOS amplifier circuit of claim 1 , wherein the first and second compensating capacitors have capacitances chosen to compensate an effect of gate-to-drain capacitances of the first and second NMOS input transistors on frequency and time responses of the CMOS amplifier circuit.

Claim 15

A CMOS amplifier circuit, comprising: a differential input circuit including differentially coupled first NMOS input transistor having first gate, drain, and source terminals and second NMOS input transistor having second gate, drain, and source terminals; a first voltage reference node; a current mirror circuit coupled to the first drain terminal, the second drain terminal, and the first voltage reference node; an output stage circuit coupled to the differential input circuit and the current mirror circuit, the output stage circuit including a signal output; a first compensating capacitor coupled between the second drain terminal and the first gate terminal; a second compensating capacitor coupled between the signal output and the second gate terminal; and a source node coupled to the first source terminal and the second source terminal, a second voltage reference node, and a bias resistor coupled between the source node and the second voltage reference node, wherein the first and second compensating capacitors have capacitances chosen to compensate an effect of gate-to-drain capacitances of the first and second NMOS input transistors on frequency and time responses of the CMOS amplifier circuit.

Claim 16

A CMOS amplifier circuit, comprising: a differential input circuit including differentially coupled first NMOS input transistor having first gate, drain, and source terminals and second NMOS input transistor having second gate, drain, and source terminals; a first voltage reference node; a current mirror circuit coupled to the first drain terminal, the second drain terminal, and the first voltage reference node; an output stage circuit coupled to the differential input circuit and the current mirror circuit, the output stage circuit including a signal output; a first compensating capacitor coupled between the second drain terminal and the first gate terminal; a second compensating capacitor coupled between the signal output and the second gate terminal; and a source node coupled to the first source terminal and the second source terminal, a second voltage reference node, and a bias resistor coupled between the source node and the second voltage reference node, wherein the first and second compensating capacitors have capacitances chosen to compensate an effect of gate-to-drain capacitances of the first and second NMOS input transistors on frequency and time responses of the CMOS amplifier circuit.

Claim 17

The CMOS amplifier circuit of claim 13 , wherein the output stage circuit has a gain of approximately one, the first and second NMOS input transistors are approximately matched transistors each having a gate-to-drain capacitance approximately equal to a matched capacitance, and the first and second compensating capacitors each have a capacitance approximately equal to the matched capacitance.