Sense amplifier with improved read access

Claim 2

A sense amplifier for an integrated circuit memory, comprising: first and second output nodes; and a pre-charge transistor coupled to the second output node and adapted to pre-charge the second output node to approximately a first power supply potential, wherein the first output node is adapted to be pre-charged to a second power supply potential, and wherein the sense amplifier is adapted to provide first and second output signals at the first and second output nodes, respectively, in response to at least a first input signal.

Claim 3

The sense amplifier of claim 1 , wherein the sense amplifier is adapted to provide first and second output signals at the first and second output nodes, respectively, in response to first and second input signals.

Claim 4

The sense amplifier of claim 2 , wherein the first and second input signals are complementary signals.

Claim 5

The sense amplifier of claim 2 , further comprising first and second input nodes adapted to receive the first and second input signals, respectively, wherein the first and second input nodes are adapted for coupling to first and second output nodes, respectively, of an integrated circuit memory cell.

Claim 6

The sense amplifier of claim 2 , further comprising first and second input nodes adapted to receive the first and second input signals, respectively, wherein the first and second input nodes are adapted for coupling, respectively, to a first integrated circuit memory cell and to a reference.

Claim 7

A memory cell and sense amplifier combination in an integrated circuit, comprising: first and second output nodes; a first transistor coupled between a first power supply node and the first output node; a second transistor coupled between the first output node and a second power supply node, the second transistor having a gate terminal coupled to a first bit line; a third transistor coupled between the first power supply node and the second output node; a fourth transistor coupled between the first power supply node and the second output node, the fourth transistor having a gate terminal coupled to a clock signal line, the fourth transistor adapted to pre-charge the second output node to approximately a potential at the first power supply node; a fifth transistor coupled between the second output node and the second power supply node, the fifth transistor having a gate terminal coupled to a second bit line; the first output node adapted to be pre-charged to approximately a potential at the second power supply node, and the sense amplifier adapted to provide first and second output signals at the first and second output nodes, respectively, in response to signals on the first and second bit lines and a clock signal on the clock signal line; and a memory cell adapted to be controllably coupled to the first bit line.

Claim 8

A memory cell and sense amplifier combination in an integrated circuit, comprising: first and second output nodes; a first transistor coupled between a first power supply node and the first output node; a second transistor coupled between the first output node and a second power supply node, the second transistor having a gate terminal coupled to a first bit line; a third transistor coupled between the first power supply node and the second output node; a fourth transistor coupled between the first power supply node and the second output node, the fourth transistor having a gate terminal coupled to a clock signal line, the fourth transistor adapted to pre-charge the second output node to approximately a potential at the first power supply node; a fifth transistor coupled between the second output node and the second power supply node, the fifth transistor having a gate terminal coupled to a second bit line; the first output node adapted to be pre-charged to approximately a potential at the second power supply node, and the sense amplifier adapted to provide first and second output signals at the first and second output nodes, respectively, in response to signals on the first and second bit lines and a clock signal on the clock signal line; and a memory cell adapted to be controllably coupled to the first bit line.

Claim 9

The memory cell and sense amplifier combination of claim 6 , wherein the memory cell comprises first and second output nodes, the first and second output nodes of the memory cell adapted to be controllably coupled to the first and second bit lines, respectively.

Claim 10

The memory cell and sense amplifier combination of claim 7 , wherein the memory cell comprises a static random access memory cell.

Claim 11

The memory cell and sense amplifier combination of claim 6 , further comprising a reference signal line adapted to be controllably coupled to the second bit line.

Claim 12

The memory cell and sense amplifier combination of claim 9 , wherein the memory cell comprises a dynamic random access memory cell.

Claim 13

The memory cell and sense amplifier combination of claim 9 , wherein the memory cell comprises a read-only memory cell.

Claim 14

The memory cell and sense amplifier combination of claim 9 , wherein the memory cell comprises a programmable read-only memory cell.

Claim 15

The memory cell and sense amplifier combination of claim 9 , wherein the memory cell comprises an erasable programmable read-only memory cell.

Claim 16

The memory cell and sense amplifier combination of claim 9 , wherein the memory cell comprises a Flash memory cell.

Claim 17

The memory cell and sense amplifier combination of claim 6 , wherein the memory cell comprises a static random access memory cell.

Claim 18

The memory cell and sense amplifier combination of claim 6 , wherein the memory cell comprises a dynamic random access memory cell.

Claim 19

The memory cell and sense amplifier combination of claim 6 , wherein the memory cell comprises a read-only memory cell.

Claim 20

The memory cell and sense amplifier combination of claim 6 , wherein the memory cell comprises a programmable read-only memory cell.

Claim 21

The memory cell and sense amplifier combination of claim 6 , wherein the memory cell comprises an erasable programmable read-only memory cell.

Claim 22

A sensing circuit, comprising: a sense amplifier adapted to receive an input signal from a memory cell and to provide a first output signal on a first output node; and an output amplifier adapted to receive the first output signal and to provide a second output signal on a second output node, wherein the sense amplifier comprises a sense amplifier pre-charge transistor coupled between a first power supply node and the first output node, said sense amplifier pre-charge transistor adapted to pre-charge the first output node to approximately a first power supply potential, and wherein the output amplifier comprises an output amplifier pre-charge transistor coupled between the first power supply node and the second output node, said output amplifier pre-charge transistor adapted to pre-charge the second output node to approximately the first power supply potential.

Claim 23

A sensing circuit, comprising: a sense amplifier adapted to receive an input signal from a memory cell and to provide a first output signal on a first output node; and an output amplifier adapted to receive the first output signal and to provide a second output signal on a second output node, wherein the sense amplifier comprises a sense amplifier pre-charge transistor coupled between a first power supply node and the first output node, said sense amplifier pre-charge transistor adapted to pre-charge the first output node to approximately a first power supply potential, and wherein the output amplifier comprises an output amplifier pre-charge transistor coupled between the first power supply node and the second output node, said output amplifier pre-charge transistor adapted to pre-charge the second output node to approximately the first power supply potential.

Claim 24

The sensing circuit of claim 20 , further comprising an output driver adapted to receive the second output signal and to provide a third output signal on a third output node, wherein the output driver comprises an output driver pre-charge transistor coupled between the first power supply node and the third output node, said output driver pre-charge transistor adapted to receive a third clock signal and pre-charge the third output node to approximately the first power supply potential.

Claim 25

The sensing circuit of claim 20 , wherein the memory cell is a static memory cell.

Claim 26

The sensing circuit of claim 20 , wherein the memory cell is a Flash memory cell.

Claim 27

The sensing circuit of claim 20 , wherein the memory cell is an EAPROM cell.

Claim 28

The sensing circuit of claim 20 , wherein the memory cell is an EPROM cell.

Claim 29

The sensing circuit of claim 20 , wherein the memory cell is a PROM cell.

Claim 30

The sensing circuit of claim 20 , wherein the memory cell is a ROM cell.

Claim 31

The sensing circuit of claim 20 , wherein the memory cell is an SRAM cell.

Claim 32

A sensing circuit, comprising: a sense amplifier adapted to receive an input signal from a memory cell and a reference signal, the sense amplifier also adapted to produce a first output signal indicative of a difference between the input signal and the reference signal; and an amplifier circuit coupled to the sense amplifier and adapted to receive the first output signal from the sense amplifier, the amplifier circuit adapted to produce an amplifier output signal on an output line, wherein the amplifier circuit comprises a pre-charge transistor coupled between a first power supply node and the output line, the pre-charge transistor adapted to pre-charge the output node to approximately a first power supply potential.

Claim 33

A sensing circuit, comprising: a sense amplifier adapted to receive an input signal from a memory cell and a reference signal, the sense amplifier also adapted to produce a first output signal indicative of a difference between the input signal and the reference signal; and an amplifier circuit coupled to the sense amplifier and adapted to receive the first output signal from the sense amplifier, the amplifier circuit adapted to produce an amplifier output signal on an output line, wherein the amplifier circuit comprises a pre-charge transistor coupled between a first power supply node and the output line, the pre-charge transistor adapted to pre-charge the output node to approximately a first power supply potential.

Claim 34

The sensing circuit of claim 29 , wherein the sense amplifier is adapted to produce first and second output signals, the first and second output signals indicative of a difference between the input signal and the reference signal.

Claim 35

The sensing circuit of claim 30 , wherein the amplifier circuit further comprises: first and second amplifier circuits, the first amplifier circuit coupled to receive the first output signal of the sense amplifier and produce a first amplifier output signal on a first output node, the first amplifier circuit having a first pre-charge transistor coupled to the first output node and adapted to pre-charge the first output node to approximately a first power supply potential, the second amplifier circuit coupled to receive the second output signal of the sense amplifier and produce a second amplifier output signal on a second output node, the second amplifier circuit having a second pre-charge transistor coupled to the second output node and adapted to pre-charge the second output node to approximately the first power supply potential.

Claim 36

The sensing circuit of claim 29 , wherein the memory cell is a dynamic memory cell.

Claim 37

The sensing circuit of claim 29 , wherein the memory cell is a dynamic random access memory cell.

Claim 38

The sensing circuit of claim 29 , wherein the memory cell is a dynamic shift register cell.

Claim 39

The sensing circuit of claim 29 , wherein the memory cell is a charge-coupled device.