US6741121B2
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Differential amplifier common mode noise compensation
Assignee: Micron Technology Inc
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Filing: 2002-08-27
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Granted: 2004-05-25
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Expires: 2022-08-27
Abstract
Abstract An amplifying circuit includes a compensation unit with a feeding forward path to reduce the effect of the common mode noise on the output signals of a differential amplifier. The compensation unit includes a capacitive network connected to input nodes and output nodes of the differential amplifier. The capacitive network provides the feeding forward path.
Inventors
- 👤 Brian W. Huber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:20
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45479; H03F3/45632; H03F3/45695
Claims Analysis
Total Claims: 56
Claim 1
Independent Claim
168 words
A circuit comprising: a differential amplifier having a first differential input node and a second differential input node for receiving differential input signals, and having a first differential output node and a second differential output node for outputting differential output signals, wherein the differential amplifier includes a first driver transistor connected to the first differential input node and the first differential output node, a second driver transistor connected to the second differential input node and the second differential output node, a source transistor connected between a second supply node and the first and second driver transistors, and at least one load transistor connected to one of the first and second differential output nodes and a compensation node; an isolation unit connected in series with a supply path of the differential amplifier between a supply node and the compensation node; and a capacitive network connected to the compensation node and the first and second differential input nodes for compensating a common mode noise affected on the differential output signals.
Claim 2
Dependent Claim
168 words
A circuit comprising: a differential amplifier having a first differential input node and a second differential input node for receiving differential input signals, and having a first differential output node and a second differential output node for outputting differential output signals, wherein the differential amplifier includes a first driver transistor connected to the first differential input node and the first differential output node, a second driver transistor connected to the second differential input node and the second differential output node, a source transistor connected between a second supply node and the first and second driver transistors, and at least one load transistor connected to one of the first and second differential output nodes and a compensation node; an isolation unit connected in series with a supply path of the differential amplifier between a supply node and the compensation node; and a capacitive network connected to the compensation node and the first and second differential input nodes for compensating a common mode noise affected on the differential output signals.
Claim 3
Dependent Claim
42 words
The circuit of claim 1 , wherein the capacitive network includes: a first capacitive element connected between the first differential input node and the compensation node; and a second capacitive element connected between the second differential input node and the compensation node.
Claim 4
Dependent Claim
18 words
The circuit of claim 2 , wherein each of the first and second capacitive elements is a capacitor.
Claim 5
Dependent Claim
22 words
The circuit of claim 3 , wherein the isolation unit includes a resistor connected between the supply node and the compensation node.
Claim 6
Dependent Claim
22 words
The circuit of claim 3 , wherein the isolation unit includes a transistor connected between the supply node and the compensation node.
Claim 7
Dependent Claim
116 words
A circuit comprising: a pair of driver transistors connected to a first differential input node and a second differential input node for receiving differential input signals; a load unit connected to the pair of driver transistors at a first differential output node and at a second differential output node for outputting differential output signals and to a compensation node; a current source connected in series with the pair of driver transistors and a supply node; an isolation unit connected in series with the load unit on a supply path between a second supply node and the compensation node; and a capacitive network connected to the compensation node and to the first and second differential input nodes.
Claim 8
Dependent Claim
116 words
A circuit comprising: a pair of driver transistors connected to a first differential input node and a second differential input node for receiving differential input signals; a load unit connected to the pair of driver transistors at a first differential output node and at a second differential output node for outputting differential output signals and to a compensation node; a current source connected in series with the pair of driver transistors and a supply node; an isolation unit connected in series with the load unit on a supply path between a second supply node and the compensation node; and a capacitive network connected to the compensation node and to the first and second differential input nodes.
Claim 9
Dependent Claim
42 words
The circuit of claim 6 , wherein the capacitive network includes: a first capacitive element connected between the first differential input node and the compensation node; and a second capacitive element connected between the second differential input node and the compensation node.
Claim 10
Dependent Claim
18 words
The circuit of claim 7 , wherein each of the first and second capacitive elements is a capacitor.
Claim 11
Dependent Claim
22 words
The circuit of claim 8 , wherein the isolation unit includes a resistor connected between the supply node and the compensation node.
Claim 12
Dependent Claim
22 words
The circuit of claim 8 , wherein the isolation unit includes a transistor connected between the supply node and the compensation node.
Claim 13
Dependent Claim
30 words
The circuit of claim 6 , wherein the load unit includes at least one transistor connected between the compensation node and each of the first and second differential output nodes.
Claim 14
Dependent Claim
28 words
The circuit of claim 6 , wherein the load unit includes a resistor connected between the compensation node and each of the first and second differential output nodes.
Claim 15
Dependent Claim
109 words
A circuit comprising: a first branch and a second branch, each of first and second branches being connected between a supply node and a common node, each of first and second branches including: a resistive element connected between the supply node and a compensation node; a load transistor connected between the compensation node and an output node; a driver transistor connected between the output node and the common node and having a gate connected to an input node to receive an input signal; a capacitive element connected between the compensation node and the input node; and a current source connected between the common node and a second supply node.
Claim 16
Dependent Claim
109 words
A circuit comprising: a first branch and a second branch, each of first and second branches being connected between a supply node and a common node, each of first and second branches including: a resistive element connected between the supply node and a compensation node; a load transistor connected between the compensation node and an output node; a driver transistor connected between the output node and the common node and having a gate connected to an input node to receive an input signal; a capacitive element connected between the compensation node and the input node; and a current source connected between the common node and a second supply node.
Claim 17
Dependent Claim
13 words
The circuit of claim 13 , wherein the resistive element is a resistor.
Claim 18
Dependent Claim
13 words
The circuit of claim 13 , wherein the capacitive element is a capacitor.
Claim 19
Dependent Claim
14 words
The circuit of claim 13 , wherein the first and second branches are symmetrical.
Claim 20
Dependent Claim
131 words
A circuit comprising: a pair of driver transistors connected to a first differential input node and a second differential input node for receiving differential input signals; a load unit connected to the pair of driver transistors at a first differential output node and at a second differential output node for outputting differential output signals and to a compensation node; a current source connected in series with the pair of driver transistors and a supply node; an isolation unit connected in series with the load unit on a supply path between a second supply node and the compensation node; a capacitive network connected to the compensation node and the first and second differential input nodes; and a control unit connected between the load unit and the first and second differential output nodes.
Claim 21
Dependent Claim
131 words
A circuit comprising: a pair of driver transistors connected to a first differential input node and a second differential input node for receiving differential input signals; a load unit connected to the pair of driver transistors at a first differential output node and at a second differential output node for outputting differential output signals and to a compensation node; a current source connected in series with the pair of driver transistors and a supply node; an isolation unit connected in series with the load unit on a supply path between a second supply node and the compensation node; a capacitive network connected to the compensation node and the first and second differential input nodes; and a control unit connected between the load unit and the first and second differential output nodes.
Claim 22
Dependent Claim
42 words
The circuit of claim 17 , wherein the control unit includes: a first resistive element connected between the load unit and the first differential output node; and a second resistive element connected between the load unit and the second differential output node.
Claim 23
Dependent Claim
86 words
The circuit of claim 17 , wherein a control unit includes a first control transistor and a second control transistor forming a differential pair, the first control transistor having a gate connected to the first and second differential output nodes through a resistive network, the second control transistor having a gate connected to an input node of the differential pair to receive a reference signal, the differential pair being connected to the load unit at a drain of one of the first and second control transistors.
Claim 24
Dependent Claim
50 words
The circuit of claim 19 , wherein the resistive network including: a first resistive element connected between the first differential output node and the a gate of first control transistor; and a second resistive element connected between the second differential output node and the gate of the second control transistor.
Claim 25
Dependent Claim
160 words
A circuit comprising: a differential amplifier having a first differential input node and a second differential input node for receiving differential input signals, and having a first differential output node and a second differential output node for outputting differential output signals, wherein the differential amplifier includes a first driver transistor connected to the first differential input node and the first differential output node, a second driver transistor connected to the second differential input node and the second differential output node, a source transistor connected between a second supply node and the first and second driver transistors, and at least one load transistor connected to one of the first and second differential output nodes and a compensation node; a capacitive network connected to the differential amplifier for reducing a common mode noise affected on the differential output signals; and a non-differential element connected to one of the first and second differential output nodes to receive one of the differential output signals.
Claim 26
Dependent Claim
160 words
A circuit comprising: a differential amplifier having a first differential input node and a second differential input node for receiving differential input signals, and having a first differential output node and a second differential output node for outputting differential output signals, wherein the differential amplifier includes a first driver transistor connected to the first differential input node and the first differential output node, a second driver transistor connected to the second differential input node and the second differential output node, a source transistor connected between a second supply node and the first and second driver transistors, and at least one load transistor connected to one of the first and second differential output nodes and a compensation node; a capacitive network connected to the differential amplifier for reducing a common mode noise affected on the differential output signals; and a non-differential element connected to one of the first and second differential output nodes to receive one of the differential output signals.
Claim 27
Dependent Claim
46 words
The circuit of claim 21 , wherein the capacitive network includes: a first capacitive element connected between the first differential input node and the compensation node of the differential amplifier; and a second capacitive element connected between the second differential input node and the compensation node.
Claim 28
Dependent Claim
18 words
The circuit of claim 22 , wherein one of the first and second capacitive elements is a capacitor.
Claim 29
Dependent Claim
29 words
The circuit of claim 21 further includes an isolation unit connected in series with a supply path of the differential amplifier between a supply node and the compensation node.
Claim 30
Dependent Claim
22 words
The circuit of claim 24 , wherein the isolation unit includes a resistor connected between the supply node and the compensation node.
Claim 31
Dependent Claim
208 words
A memory device comprising: a plurality of memory cells; and an address path, a data path, and a control path, all paths connected to the memory cells, wherein at least one of the paths includes an input buffer, the input buffer including: a differential amplifier having a first differential input node and a second amplifier input node for receiving differential input signals, and having a first differential output node and a second differential output node for outputting differential output signals, wherein the differential amplifier includes a first driver transistor connected to the first differential input node and the first differential output node, a second driver transistor connected to the second differential input node and the second differential output node, a source transistor connected between a second supply node and the first and second driver transistors, and at least one load transistor connected to one of the first and second differential output nodes and a compensation node; an isolation unit connected in series with a supply path of the differential amplifier between a supply node and the compensation node; and a capacitive network connected to the compensation node and to the first and second differential input nodes for compensating a common mode noise affected on the differential output signals.
Claim 32
Dependent Claim
208 words
A memory device comprising: a plurality of memory cells; and an address path, a data path, and a control path, all paths connected to the memory cells, wherein at least one of the paths includes an input buffer, the input buffer including: a differential amplifier having a first differential input node and a second amplifier input node for receiving differential input signals, and having a first differential output node and a second differential output node for outputting differential output signals, wherein the differential amplifier includes a first driver transistor connected to the first differential input node and the first differential output node, a second driver transistor connected to the second differential input node and the second differential output node, a source transistor connected between a second supply node and the first and second driver transistors, and at least one load transistor connected to one of the first and second differential output nodes and a compensation node; an isolation unit connected in series with a supply path of the differential amplifier between a supply node and the compensation node; and a capacitive network connected to the compensation node and to the first and second differential input nodes for compensating a common mode noise affected on the differential output signals.
Claim 33
Dependent Claim
43 words
The memory device of claim 26 , wherein the capacitive network includes: a first capacitive element connected between the first differential input node and the compensation node; and a second capacitive element connected between the second differential input node and the compensation node.
Claim 34
Dependent Claim
19 words
The memory device of claim 27 , wherein each of the first and second capacitive elements is a capacitor.
Claim 35
Dependent Claim
23 words
The memory device of claim 28 , wherein the isolation unit includes a resistor connected between the supply node and the compensation node.
Claim 36
Dependent Claim
23 words
The memory device of claim 28 , wherein the isolation unit includes a transistor connected between the supply node and the compensation node.
Claim 37
Independent Claim
221 words
A system comprising: a processor; and a memory device connected to the processor, the memory device including: a plurality of memory cells; and an address path, a data path, and a control path, all paths connected to the memory cells, wherein at least one of the paths includes an input buffer, the input buffer including: a differential amplifier having a first differential input node and a second amplifier input node for receiving differential input signals, and having a first differential output node and a second differential output node for outputting differential output signals, wherein the differential amplifier includes a first driver transistor connected to the first differential input node and the first differential output node, a second driver transistor connected to the second differential input node and the second differential output node, a source transistor connected between a second supply node and the first and second driver transistors, and at least one load transistor connected to one of the first and second differential output nodes and a compensation node; an isolation unit connected in series with a supply path of the differential amplifier between a supply node and the compensation node; and a capacitive network connected to the compensation node and to the first and second differential input nodes for compensating a common mode noise affected on the differential output signals.
Claim 38
Independent Claim
221 words
A system comprising: a processor; and a memory device connected to the processor, the memory device including: a plurality of memory cells; and an address path, a data path, and a control path, all paths connected to the memory cells, wherein at least one of the paths includes an input buffer, the input buffer including: a differential amplifier having a first differential input node and a second amplifier input node for receiving differential input signals, and having a first differential output node and a second differential output node for outputting differential output signals, wherein the differential amplifier includes a first driver transistor connected to the first differential input node and the first differential output node, a second driver transistor connected to the second differential input node and the second differential output node, a source transistor connected between a second supply node and the first and second driver transistors, and at least one load transistor connected to one of the first and second differential output nodes and a compensation node; an isolation unit connected in series with a supply path of the differential amplifier between a supply node and the compensation node; and a capacitive network connected to the compensation node and to the first and second differential input nodes for compensating a common mode noise affected on the differential output signals.
Claim 39
Dependent Claim
42 words
The system of claim 31 , wherein the capacitive network includes: a first capacitive element connected between the first differential input node and the compensation node; and a second capacitive element connected between the second differential input node and the compensation node.
Claim 40
Dependent Claim
18 words
The system of claim 32 , wherein each of the first and second capacitive elements is a capacitor.
Claim 41
Dependent Claim
22 words
The system of claim 33 , wherein the isolation unit includes a resistor connected between the supply node and the compensation node.
Claim 42
Dependent Claim
22 words
The system of claim 33 , wherein the isolation unit includes a transistor connected between the supply node and the compensation node.
Claim 43
Independent Claim
148 words
A method comprising: receiving differential input signals at plurality of input nodes of a differential amplifier; generating differential output signals at a plurality of output nodes of the differential amplifier, the differential amplifier having a first driver transistor connected to a first output node of the plurality of output nodes and a first input node of the plurality of input nodes, a second driver transistor connected to a second output node of the plurality of output nodes and a second input node of plurality of input nodes, a source transistor connected between a second supply node and the first and second driver transistors, and at least one load transistor connected to one of the first and second output nodes; and compensating a common mode noise affected on the differential output signals using a network with a feed forward path connected to at least one of the input nodes.
Claim 44
Independent Claim
148 words
A method comprising: receiving differential input signals at plurality of input nodes of a differential amplifier; generating differential output signals at a plurality of output nodes of the differential amplifier, the differential amplifier having a first driver transistor connected to a first output node of the plurality of output nodes and a first input node of the plurality of input nodes, a second driver transistor connected to a second output node of the plurality of output nodes and a second input node of plurality of input nodes, a source transistor connected between a second supply node and the first and second driver transistors, and at least one load transistor connected to one of the first and second output nodes; and compensating a common mode noise affected on the differential output signals using a network with a feed forward path connected to at least one of the input nodes.
Claim 45
Dependent Claim
21 words
The method of claim 36 , wherein compensating includes connecting a capacitive network to the input nodes of the differential amplifier.
Claim 46
Dependent Claim
25 words
The method of claim 37 , wherein compensating includes adding a resistive load between a compensation node and a supply node of the differential amplifier.
Claim 47
Dependent Claim
30 words
The method of claim 36 , wherein compensating includes introducing a capacitance between a compensation node of the differential amplifier and each of the input nodes of the differential amplifier.
Claim 48
Dependent Claim
25 words
The method of claim 39 , wherein compensating further includes adding a resistance between the compensation node and a supply node of the differential amplifier.
Claim 49
Independent Claim
166 words
A method comprising: receiving a first input signal and a second signal at a pair of input nodes of a differential amplifier; generating a first output signal at a first output node of the differential amplifier; generating a second output signal at a second output node of the differential amplifier, the differential amplifier having a first driver transistor connected to the first output node and a first input node of the pair of input nodes, a second driver transistor connected to the second output node and a second input node of the pair of input nodes, a source transistor connected between a second supply node and the first and second driver transistors, and at least one load transistor connected to one of the first and second output nodes; and compensating a common mode noise affected on the first output signal and the second output signal using a network with a feed forward path connected to at least one input node of the pair of input nodes.
Claim 50
Independent Claim
166 words
A method comprising: receiving a first input signal and a second signal at a pair of input nodes of a differential amplifier; generating a first output signal at a first output node of the differential amplifier; generating a second output signal at a second output node of the differential amplifier, the differential amplifier having a first driver transistor connected to the first output node and a first input node of the pair of input nodes, a second driver transistor connected to the second output node and a second input node of the pair of input nodes, a source transistor connected between a second supply node and the first and second driver transistors, and at least one load transistor connected to one of the first and second output nodes; and compensating a common mode noise affected on the first output signal and the second output signal using a network with a feed forward path connected to at least one input node of the pair of input nodes.
Claim 51
Dependent Claim
23 words
The method of claim 41 , wherein compensating includes applying a capacitive network to the pair of input nodes of the differential amplifier.
Claim 52
Dependent Claim
24 words
The method of claim 42 , wherein compensating includes applying a resistance between a compensation node and a supply node of the differential amplifier.
Claim 53
Dependent Claim
32 words
The method of claim 43 , wherein generating a first output signal and generating a second output signal includes driving a non-differential element using one of the first and second output signals.
Claim 54
Dependent Claim
34 words
The method of claim 41 , wherein compensating includes introducing a capacitance between a compensation node of the differential amplifier and each input node of the pair of input nodes of the differential amplifier.
Claim 55
Dependent Claim
25 words
The method of claim 45 , wherein compensating further includes introducing a resistance between the compensation node and a supply node of the differential amplifier.
Claim 56
Dependent Claim
32 words
The method of claim 46 , wherein generating a first output signal and generating a second output signal includes driving a non-differential element using one of the first and second output signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2007-05-25 | 2007-11-24 | 2008-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-05-25 | 2011-11-24 | 2012-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-05-25 | 2015-11-24 | 2016-05-25 | $7700.00 | Window Closed / Lapsed |