Gain controlled differential amplifier circuit

Claim 2

A gain-controlled differential amplifier circuit including in combination: first and second transistors, each having a base, collector and emitter; first and second voltage supply terminals adapted for connection across a source of direct current voltage; first circuit means coupling the collectors of said first and second transistorS with said first voltage supply terminal; means for applying input signals to the bases of said transistors; first and second variable impedance means coupled together at a first junction and connected in series between the emitters of said first and second transistors; second circuit means coupling said first junction with said second voltage supply terminal; means for supplying a gain control voltage; and means for varying the impedance of the first and second variable impedance means in response to said gain control voltage.

Claim 3

The combination according to claim 1 wherein said first and second variable impedance means have the same impedance and said means for varying the impedance of said first and second variable impedance means causes said impedance of both of said impedance means to be varied in the same amount simultaneously.

Claim 4

The combination according to claim 1 wherein said second circuit means comprises: a current source including a third transistor, having a base, collector and emitter, the collector of said third transistor being connected with said junction, the emitter of said third transistor being connected in circuit with said second voltage supply terminal; and the base of said third transistor being coupled with a source of biasing potential.

Claim 5

The combination according to claim 3 wherein said first circuit means includes fourth and fifth transistors, connected in cascode circuits respectively, between the collectors of said first and second transistors and said first voltage supply terminal.

Claim 6

A gain-controlled differential amplifier circuit including in combination: first and second voltage supply terminals adapted for connection across a source of operating potential; first and second transistors, each having a collector, base and emitter; first circuit means connecting the collectors of said first and second transistors with said first voltage supply terminal; means for applying input signals to the bases of said first and second transistors; first and second resistance means coupled together at a first junction and connected in series between the emitter of said first and second transistors; third and fourth transistors, each having a collector base and emitter, with the collector-emitter path of said third transistor connected in parallel with said first resistance means, and the collector-emitter path of said fourth transistor connected in parallel with said second resistance means; control circuit means coupled with the bases of said third and fourth transistors for varying the conductivity thereof in response to a gain control voltage; means for supplying a gain control voltage to said control circuit means; and current source means coupling said first junction with said second voltage supply terminal.

Claim 7

A gain-controlled differential amplifier circuit including in combination: first and second voltage supply terminals adapted for connection across a source of operating potential; first and second transistors, each having a collector, base and emitter; first circuit means connecting the collectors of said first and second transistors with said first voltage supply terminal; means for applying input signals to the bases of said first and second transistors; first and second resistance means coupled together at a first junction and connected in series between the emitter of said first and second transistors; third and fourth transistors, each having a collector base and emitter, with the collector-emitter path of said third transistor connected in parallel with said first resistance means, and the collector-emitter path of said fourth transistor connected in parallel with said second resistance means; control circuit means coupled with the bases of said third and fourth transistors for varying the conductivity thereof in response to a gain control voltage; means for supplying a gain control voltage to said control circuit means; and current source means coupling said first junction with said second voltage supply terminal.

Claim 8

The combination according to claim 5 wherein the collector of said third transistor is connected to the emitter of said first transistor, the collector of said fourth transistor is connected to the emitter of said second transistor, the emitters of the third and fourth transistors are connected together at said first junction, and the bases of said third and fourth transistors are coupled with the output of said control circuit means, with said third and fourth transistors being driven between cutoff and saturation by the output of said control circuit means.

Claim 9

The combination according to claim 6 wherein said current source means includes third resistance means and a first current source transistor, having a base, collector and emitter, wit the collector of said first current source transistor being connected to said first junction and the emitter of said first current source transistor being connected through said third resistance means to said second voltage supply terminal, the combination further including means for supplying an operating potential to the base of said first current source transistor.

Claim 10

The combination according to claim 7 further including fourth resistance means, wherein said control circuit means includes a second current source transistor, having a collector, base, and emitter, the collector thereof being coupled through said fourth resistance means to a voltage supply terminal, the collector of said second current source transistor also being coupled in circuit with the bases of said third and fourth transistors, the emitter electrode of said second current source transistor being coupled in circuit with the emitter electrode of said first current source transistor, and the base electrode of said second current source transistor being coupled with said means for supplying gain control voltage, thereby causing the conductivity of said second current source transistor to vary in accordance with said gain control voltage.

Claim 11

The combination according to claim 8 wherein said first circuit means includes fifth and sixth transistors, each having a base, collector and emitter, the collector-emitter path of said fifth transistor connected in cascode circuit between the collector of said first transistor and said first voltage supply terminal, the collector-emitter path of said sixth transistor connected in cascode circuit between the collector of said second transistor and said first voltage supply terminal and means for providing a bias potential to the bases of said fifth and sixth transistors.

Claim 12

The combination according to claim 8 further including coupling resistance means and wherein the emitter of said first current source transistor is connected with said third resistance means at a third junction and the emitter of the second current source transistor is connected through said coupling resistance means to said third junction.

Claim 13

The combination according to claim 10 wherein all of said transistors are of the same conductivity type.