US6064613A
Expired / Lapsed
US
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Pre-sense amplifier with reduced output swing
Assignee: Etron Technology Inc
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Filing: 1998-12-28
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Granted: 2000-05-16
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Expires: 2018-12-28
Abstract
Abstract A fast CMOS sense amplifier for semiconductor memories is disclosed. The memory sense amplifier configuration is comprised of differential pre-sense amplifier stage and a sense amplifier second stage. The pre-sense amplifier stage is composed of two sections with feedback between the sections which reduces the output swing by means of a clamping action, therefore improving output switching recovery time in response to differential input. The feedback between the sections is provided by cross connecting the sub outputs of each section to the gate of a clamping transistor at each section. The reduced recovery time produces reduced delay at the output which speeds up the operation of the sense amplifier. Additionally, the clamping devices have the effect of reducing the average DC current in the pre-sense amplifier.
Inventors
- 👤 Gyh-Bin Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:46
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/062; G11C2207/00; G11C2207/06; G11C2207/063
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
296 words
A two stage memory sense amplifier where the second stage is an output buffer amplifier and where the first stage is a semiconductor memory pre-sense amplifier having a pair of differential inputs and a pair of complementary outputs and where the memory pre-sense amplifier consists of two sections, each section having a pair of differential input nodes and a pair of complementary output nodes which provide feedback between said sections so as to result in an output response with reduced delay comprising: a first and second memory data line connected respectively to a first and second input of a first pre-sense amplifier section; a first and second memory data line connected respectively to a second and first input of a second pre-sense amplifier section; a first output node and a complementary second output node on said first pre-sense amplifier section where said first output node is a first output of said memory pre-sense amplifier; a first output node and a complementary second output node on said second pre-sense amplifier section where said first output node is a second output of said memory pre-sense amplifier; a mechanism for feedback implementation on each of said pre-sense amplifier sections; wherein said mechanism for feedback implementation on said first pre-sense amplifier section is connected to said second output node of said second pre-sense amplifier section; wherein said mechanism for feedback implementation on said second pre-sense amplifier section is connected to said second output of said first pre-sense amplifier section; and wherein said pre-sense amplifier connections provide a feedback such as to limit the signal excursion on said first and second memory pre-sense amplifier outputs thereby reducing the delay of the output response of said memory pre-sense amplifier to an input signal on the differential inputs of said memory pre-sense amplifier.
Claim 2
Dependent Claim
296 words
A two stage memory sense amplifier where the second stage is an output buffer amplifier and where the first stage is a semiconductor memory pre-sense amplifier having a pair of differential inputs and a pair of complementary outputs and where the memory pre-sense amplifier consists of two sections, each section having a pair of differential input nodes and a pair of complementary output nodes which provide feedback between said sections so as to result in an output response with reduced delay comprising: a first and second memory data line connected respectively to a first and second input of a first pre-sense amplifier section; a first and second memory data line connected respectively to a second and first input of a second pre-sense amplifier section; a first output node and a complementary second output node on said first pre-sense amplifier section where said first output node is a first output of said memory pre-sense amplifier; a first output node and a complementary second output node on said second pre-sense amplifier section where said first output node is a second output of said memory pre-sense amplifier; a mechanism for feedback implementation on each of said pre-sense amplifier sections; wherein said mechanism for feedback implementation on said first pre-sense amplifier section is connected to said second output node of said second pre-sense amplifier section; wherein said mechanism for feedback implementation on said second pre-sense amplifier section is connected to said second output of said first pre-sense amplifier section; and wherein said pre-sense amplifier connections provide a feedback such as to limit the signal excursion on said first and second memory pre-sense amplifier outputs thereby reducing the delay of the output response of said memory pre-sense amplifier to an input signal on the differential inputs of said memory pre-sense amplifier.
Claim 3
Dependent Claim
30 words
The semiconductor memory sense amplifier described in claim 1 further comprising: a second sense amplifier stage with inputs connected to said first and second outputs of said memory pre-sense amplifier.
Claim 4
Dependent Claim
102 words
The semiconductor memory pre-sense amplifier of claim 1, wherein said mechanism for feedback implementation of the first and second pre-sense amplifier sections comprises: a first MOS transistor device on the first pre-sense amplifier section wherein the gate of said first MOS transistor device of the first pre-sense amplifier section is connected to said second output node of said second pre-sense amplifier section; and a second MOS transistor device on the second pre-sense amplifier section wherein the gate of said second MOS transistor device of the second pre-sense amplifier section is connected to said second output node of said first pre-sense amplifier section.
Claim 5
Dependent Claim
18 words
The semiconductor memory pre-sense amplifier of claim 3 wherein; a current-sense amplifier has said mechanism for feedback implementation.
Claim 6
Dependent Claim
18 words
The semiconductor memory pre-sense amplifier of claim 3 wherein; a voltage-sense amplifier has said mechanism for feedback implementation.
Claim 7
Dependent Claim
51 words
The semiconductor memory pre-sense amplifier of claim 4 having two current-sense amplifier sections wherein each section receives complementary input signals from a semiconductor memory and provides the pre-sense amplifier section first output node and the pre-sense amplifier section complementary second output node used to provide the feedback between the two sections.
Claim 8
Dependent Claim
36 words
The semiconductor memory pre-sense amplifier of claim 4 wherein said first and said second MOS transistor devices provide a clamping function which respectively limits the output signal excursion of each section of said memory pre-sense amplifier.
Claim 9
Dependent Claim
136 words
A semiconductor memory pre-sense amplifier comprising: a first and second memory data line connected to first and second inputs of first and second pre-sense amplifier sections; a first output node and a complementary second output node on each of said pre-sense amplifier sections; an output clamping first MOS transistor device of the first pre-sense amplifier section wherein the connection to the gate of said output clamping first MOS transistor device of the first pre-sense amplifier section is connected to the second output node of the second pre-sense amplifier section; and an output clamping second MOS transistor device of the second pre-sense amplifier section wherein the connection to the gate of said output clamping second MOS transistor device of the second pre-sense amplifier section is connected to the second output node of the first pre-sense amplifier section.
Claim 10
Dependent Claim
136 words
A semiconductor memory pre-sense amplifier comprising: a first and second memory data line connected to first and second inputs of first and second pre-sense amplifier sections; a first output node and a complementary second output node on each of said pre-sense amplifier sections; an output clamping first MOS transistor device of the first pre-sense amplifier section wherein the connection to the gate of said output clamping first MOS transistor device of the first pre-sense amplifier section is connected to the second output node of the second pre-sense amplifier section; and an output clamping second MOS transistor device of the second pre-sense amplifier section wherein the connection to the gate of said output clamping second MOS transistor device of the second pre-sense amplifier section is connected to the second output node of the first pre-sense amplifier section.
Claim 11
Dependent Claim
47 words
The semiconductor memory pre-sense amplifier of claim 8 wherein each of said pre-sense amplifier sections is a current-sense amplifier comprising; an output clamping first MOS transistor device in said first pre-sense amplifier section; and an output clamping second MOS transistor device in said second pre-sense amplifier section.
Claim 12
Dependent Claim
47 words
The semiconductor memory pre-sense amplifier of claim 8 wherein each of said pre-sense amplifier sections is a voltage-sense amplifier comprising; an output clamping first MOS transistor device in said first pre-sense amplifier section; and an output clamping second MOS transistor device in said second pre-sense amplifier section.
Claim 13
Dependent Claim
28 words
The semiconductor memory pre-sense amplifier of claim 8 wherein the said output clamping MOS transistor devices reduce the average DC current in each of said pre-sense amplifier sections.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-16 | 2003-11-15 | 2004-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-16 | 2007-11-15 | 2008-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-16 | 2011-11-15 | 2012-05-16 | $7700.00 | Window Closed / Lapsed |