US5412607A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Oki Electric Industry Co Ltd
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Filing: 1994-05-25
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Granted: 1995-05-02
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Expires: 2014-05-25
Abstract
Abstract A semiconductor memory device according to the present invention includes a first and second bit lines; a word line; a memory cell electrically connected to the first and second bit lines and the word line; a first current sense amplifier for reducing a potential level of a current flowing in the first and second bit lines and including diode-connected first and second P-type transistors, third and fourth N-type transistors series-connected to the first and second P-type transistors respectively and a fifth N-type transistor connected to the third and fourth N-type transistors, the first P-type transistor having a control electrode electrically connected to a control electrode of the fourth N-type transistor and the second P-type transistor having a control electrode electrically connected to a control electrode of the third N-type transistor; and a second sense amplifier electrically connected to an output of the first current sense amplifier, for amplifying the amplitude of a potential applied between the first and second bit lines.
Inventors
- 👤 Susumu Kusaba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 18:41
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C5/00; G11C5/06; G11C2207/00; G11C2207/06; G11C2207/063
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
309 words
A semiconductor memory device comprising: first and second bit lines; a word line; a memory cell electrically connected to said first and second bit lines and said word line; a first current sense amplifier for reducing a potential level of a current flowing in said first and second bit lines and comprising first and second P-type transistors each having first and second main electrodes and a control electrode and third, fourth and fifth N-type transistors each having first and second main electrodes and a control electrode, said first main electrode of said first P-type transistor being connected electrically to said first bit line, said second main electrode of said first P-type transistor being connected to said second main electrode of said third N-type transistor through a first node and said control electrode of said first P-type transistor being connected to said second main electrode of said third N-type transistor through the first node and connected to said control electrode of said fourth N-type transistor, said first main electrode of said second P-type transistor being connected to said second bit line, said second main electrode of said second P-type transistor being connected to said second main electrode of said fourth N-type transistor through a second node and said control electrode of said second P-type transistor being connected to said second main electrode of said fourth N-type transistor through the second node and connected to said control electrode of said third N-type transistor, said first main electrodes of said third and fourth N-type transistors being connected to said second main electrode of said fifth N-type transistor, and said first main electrode of said fifth N-type transistor being connected to an earth; and a second sense amplifier electrically connected to an output of said first sense amplifier, for amplifying the amplitude of a potential applied between said first and second bit lines.
Claim 2
Dependent Claim
309 words
A semiconductor memory device comprising: first and second bit lines; a word line; a memory cell electrically connected to said first and second bit lines and said word line; a first current sense amplifier for reducing a potential level of a current flowing in said first and second bit lines and comprising first and second P-type transistors each having first and second main electrodes and a control electrode and third, fourth and fifth N-type transistors each having first and second main electrodes and a control electrode, said first main electrode of said first P-type transistor being connected electrically to said first bit line, said second main electrode of said first P-type transistor being connected to said second main electrode of said third N-type transistor through a first node and said control electrode of said first P-type transistor being connected to said second main electrode of said third N-type transistor through the first node and connected to said control electrode of said fourth N-type transistor, said first main electrode of said second P-type transistor being connected to said second bit line, said second main electrode of said second P-type transistor being connected to said second main electrode of said fourth N-type transistor through a second node and said control electrode of said second P-type transistor being connected to said second main electrode of said fourth N-type transistor through the second node and connected to said control electrode of said third N-type transistor, said first main electrodes of said third and fourth N-type transistors being connected to said second main electrode of said fifth N-type transistor, and said first main electrode of said fifth N-type transistor being connected to an earth; and a second sense amplifier electrically connected to an output of said first sense amplifier, for amplifying the amplitude of a potential applied between said first and second bit lines.
Claim 3
Dependent Claim
41 words
The semiconductor memory device according to claim 1, further comprising a first pull-up P-type transistor electrically connected to an input of said first bit line and a second pull-up P-type transistor electrically connected to an input of said second bit line.
Claim 4
Dependent Claim
155 words
A semiconductor memory device comprising: first and second bit lines; a word line; a memory cell electrically connected to said first and second bit lines and said word line; a first current sense amplifier for reducing a potential level of a current flowing in said first and second bit lines and comprising diode-connected first and second P-type transistors, third and fourth N-type transistors series-connected to said first and second P-type transistors respectively and a fifth N-type transistor connected to said third and fourth N-type transistors, said first P-type transistor having a control electrode electrically connected to a control electrode of said fourth N-type transistor and said second P-type transistor having a control electrode electrically connected to a control electrode of said third N-type transistor; and a second sense amplifier electrically connected to an output of said first current sense amplifier, for amplifying the amplitude of a potential applied between said first and second bit lines.
Claim 5
Dependent Claim
155 words
A semiconductor memory device comprising: first and second bit lines; a word line; a memory cell electrically connected to said first and second bit lines and said word line; a first current sense amplifier for reducing a potential level of a current flowing in said first and second bit lines and comprising diode-connected first and second P-type transistors, third and fourth N-type transistors series-connected to said first and second P-type transistors respectively and a fifth N-type transistor connected to said third and fourth N-type transistors, said first P-type transistor having a control electrode electrically connected to a control electrode of said fourth N-type transistor and said second P-type transistor having a control electrode electrically connected to a control electrode of said third N-type transistor; and a second sense amplifier electrically connected to an output of said first current sense amplifier, for amplifying the amplitude of a potential applied between said first and second bit lines.
Claim 6
Dependent Claim
41 words
The semiconductor memory device according to claim 3, further comprising a first pull-up P-type transistor electrically connected to an input of said first bit line and a second pull-up P-type transistor electrically connected to an input of said second bit line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-01 | 1998-10-31 | 1999-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-01 | 2002-10-31 | 2003-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-01 | 2006-10-31 | 2007-05-02 | $7700.00 | Window Closed / Lapsed |