US5325335A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memories and amplifiers suitable for low voltage power supplies
Assignee: INTERGRATED DEVICE TECHNOLOGY Inc - A CORP OF
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Filing: 1992-06-05
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Granted: 1994-06-28
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Expires: 2012-06-05
Abstract
Abstract A sense amplifier for a static memory includes two pull-up transistors. The gate of each transistor is coupled to the drain of the other transistor. A circuitry is provided for precharging the drains of both pull-up transistors to a selected voltage such that by the start of the tracking stage of the amplifier, both pull-up transistors are off. If the tracking stage is long enough, one pull-up transistor turns on while the other one remains off, so that before the start of the sensing stage both pull-up transistors reach their final ON/OFF states. Hence the amplifier is fast and power efficient. The memory bit lines are precharged to VCC before the tracking stage, improving the read-disturb immunity and hence allowing a wider range of voltages on the bit lines and the sense amplifier inputs. The noise immunity and tolerance to temperature process variations are improved as a result. The high noise immunity make the amplifier and the memory suitable for integration with noisy circuits such as CPUs. High speed, high power efficiency, high noise immunity, high tolerance to temperature and process variations and high permissible range of bit line voltages make the memory and the amplifier suitable for low-voltage power supplies such as VCC=3.0 V supplies used in lap-top, notebook, sub-note book, and hand-held computers.
Inventors
- 👤 Michael A. Ang
- 👤 David J. Pilling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:00
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/065; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
208 words
A method of reading a memory cell, comprising the steps of: precharging complementary bit lines B1 and B2 to a predetermined voltage; tracking two complementary voltages, which represent a state of said memory cell, by said bit lines B1 and B2 so that said bit line B1 tracks one of said two voltages and said bit line B2 tracks the other one of said two voltages, wherein each of said two voltages is between predetermined values V1 and V2; tracking voltages on said bit lines B1 and B2 by a sense amplifier, wherein said step of tracking two complementary voltages by the bit lines terminates before this step of tracking of voltages on said bit lines by said sense amplifier terminates; if, during said step of tracking bit line voltages by said sense amplifier, the voltage on said bit line B1 is closer to said value V1 than a predetermined amount, then pulling the voltage on said bit line B2 towards said value V2; and if, during said step of tracking bit line voltages by said sense amplifier, the voltage on said bit line B2 is closer to said value V1 than said predetermined amount, then pulling the voltage on said bit line B1 towards said value V2.
Claim 2
Independent Claim
208 words
A method of reading a memory cell, comprising the steps of: precharging complementary bit lines B1 and B2 to a predetermined voltage; tracking two complementary voltages, which represent a state of said memory cell, by said bit lines B1 and B2 so that said bit line B1 tracks one of said two voltages and said bit line B2 tracks the other one of said two voltages, wherein each of said two voltages is between predetermined values V1 and V2; tracking voltages on said bit lines B1 and B2 by a sense amplifier, wherein said step of tracking two complementary voltages by the bit lines terminates before this step of tracking of voltages on said bit lines by said sense amplifier terminates; if, during said step of tracking bit line voltages by said sense amplifier, the voltage on said bit line B1 is closer to said value V1 than a predetermined amount, then pulling the voltage on said bit line B2 towards said value V2; and if, during said step of tracking bit line voltages by said sense amplifier, the voltage on said bit line B2 is closer to said value V1 than said predetermined amount, then pulling the voltage on said bit line B1 towards said value V2.
Claim 3
Dependent Claim
144 words
A memory comprising: one or more columns of memory cells; one or more bit lines for tracking voltages indicative of states of said memory cells; one or more word lines for connecting memory cells to respective bit lines; a sense amplifier for amplifying voltages on said bit lines, said sense amplifier having, in every read operation, a tracking stage during which said sense amplifier tracks voltages on one or more bit lines; and means for asserting, during a read operation, a word line to allow one or more selected bit lines to track one or more voltages indicative of the state of a selected memory cell, said means deasserting the asserted word line before the end of the amplifier tracking stage of said read operation so as to isolate the bit lines from the memory cells before the end of the amplifier tracking stage.
Claim 4
Dependent Claim
144 words
A memory comprising: one or more columns of memory cells; one or more bit lines for tracking voltages indicative of states of said memory cells; one or more word lines for connecting memory cells to respective bit lines; a sense amplifier for amplifying voltages on said bit lines, said sense amplifier having, in every read operation, a tracking stage during which said sense amplifier tracks voltages on one or more bit lines; and means for asserting, during a read operation, a word line to allow one or more selected bit lines to track one or more voltages indicative of the state of a selected memory cell, said means deasserting the asserted word line before the end of the amplifier tracking stage of said read operation so as to isolate the bit lines from the memory cells before the end of the amplifier tracking stage.
Claim 5
Dependent Claim
66 words
The memory of claim 2 wherein: during said tracking stage, said amplifier is connected to one or more bit lines but is disabled from amplifying voltages on said bit lines; and said amplifier has a sensing stage following the tracking stage, for amplifying the voltages received from one or more selected bit lines, wherein during said sensing stage said amplifier is disconnected from said bit lines.
Claim 6
Dependent Claim
71 words
The memory of claim 2 further comprising means for precharging said bit lines to a predetermined voltage at the start of every read operation, wherein said means deasserting of a word line before the end of the amplifier tracking stage reduced a bit line voltage swing during the tracking stage thereby; (1) saving power during the next precharge by said precharging means, and (2) increasing the speed of the next precharge.
Claim 7
Dependent Claim
37 words
The memory of claim 2 wherein said means deasserting of a word line before the end of the tracking stage isolates the memory cells from any noise on the bit lines thereby improving the memory noise immunity.
Claim 8
Dependent Claim
45 words
The memory of claim 2 further comprising means for precharging the bit lines to a predetermined voltage before each tracking stage and equalizing the bit line voltages before each tracking state, wherein said means for precharging the equalizing is turned off during each tracking stage.
Claim 9
Dependent Claim
33 words
The memory of claim 2, said memory comprising two complementary bit lines for each column of memory cells, wherein said sense amplifier is for amplifying a differential voltage on two complementary bit lines.
Claim 10
Independent Claim
141 words
A method of reading a memory having one or more columns of memory cells, said method comprising the steps of: asserting a word line to connect a selected memory cell to one or more bit lines, and tracking by said one or more bit lines a state of said selected memory cell; during at least a part of said asserting and tracking step, tracking voltages on said one or more bit lines by a sense amplifier; deasserting said word line to disconnect said one or more bit lines from said selected memory cell; after deasserting said word line, continuing to track said voltages on said one or more bit lines by said sense amplifier; and disconnecting said one or more bit lines from said sense amplifier and amplifying voltages received by said sense amplifier from said one or more bit lines.
Claim 11
Independent Claim
141 words
A method of reading a memory having one or more columns of memory cells, said method comprising the steps of: asserting a word line to connect a selected memory cell to one or more bit lines, and tracking by said one or more bit lines a state of said selected memory cell; during at least a part of said asserting and tracking step, tracking voltages on said one or more bit lines by a sense amplifier; deasserting said word line to disconnect said one or more bit lines from said selected memory cell; after deasserting said word line, continuing to track said voltages on said one or more bit lines by said sense amplifier; and disconnecting said one or more bit lines from said sense amplifier and amplifying voltages received by said sense amplifier from said one or more bit lines.
Claim 12
Dependent Claim
73 words
The method of claim 8 further comprising, before said step of asserting a word line, the step of precharging said bit lines to a predetermined voltage, wherein said deasserting of said word line while continuing to track the bit line voltages by said sense amplifier reduces the voltage swing on said one or more bit lines thereby saving power during a precharging step of the next read operation and increasing the precharging speed.
Claim 13
Dependent Claim
39 words
The method of claim 8 wherein said deasserting of said word line while continuing to track the bit line voltages by said sense amplifier isolates the selected memory cell from any noise on said one or more bit lines.
Claim 14
Dependent Claim
17 words
The method of claim 8 wherein said one or more bit lines comprise two complementary bit lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-27 | 1997-12-27 | 1998-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-27 | 2001-12-27 | 2002-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-27 | 2005-12-27 | 2006-06-28 | $7700.00 | Window Closed / Lapsed |