Single-ended input to differential-ended output low noise amplifier

Claim 2

A single-ended input to differential-ended output amplifier circuit, comprising: an amplifier for amplifying an input signal into an amplified signal, comprising: an input end for receiving the input signal; and a first output end; and a single-ended input to differential-ended output conversion circuit to convert the amplified signal to a differential signal pair, comprising: a first transistor for receiving the amplified signal having a gate coupled to the first output end, a first terminal coupled to a second output end, and a second terminal coupled to a first node; a second transistor having a gate, a first terminal coupled to a third output end, and a second terminal coupled to the first node; a first capacitor coupled between the second output end and the gate of the second transistor; a first resistor coupled between the second output end and a voltage source; a second resistor coupled between the third output end and the voltage source; and a current source coupled between the first node and a ground, wherein the amplifier further comprises: a first inductor coupled to the input end; a second capacitor coupled between the first inductor and a second node; a second inductor coupled between the voltage source and the first output end; a third transistor having a gate coupled to the second node, a first terminal coupled to the first output end, and a second terminal; and a third inductor coupled between the second terminal of the third transistor and the ground.

Claim 3

The single-ended input to differential-ended output amplifier circuit as claimed in claim 1 , further comprising an antenna for receiving the input signal.

Claim 4

The single-ended input to differential-ended output amplifier circuit as claimed in claim 2 , wherein the antenna is a single-ended antenna.

Claim 5

The single-ended input to differential-ended output amplifier circuit as claimed in claim 1 , wherein the input signal is a radio frequency signal.

Claim 6

The single-ended input to differential-ended output amplifier circuit as claimed in claim 1 , further comprising a third capacitor coupled between the first output end and the single-ended input to differential-ended output conversion circuit.

Claim 7

The single-ended input to differential-ended output amplifier circuit as claimed in claim 1 , wherein the amplifier is a single-ended input to single-ended output amplifier.

Claim 8

The single-ended input to differential-ended output amplifier circuit as claimed in claim 6 , wherein the amplifier is a low noise amplifier.

Claim 9

The single-ended input to differential-ended output amplifier circuit as claimed in claim 7 , wherein the amplifier is a cascade amplifier.

Claim 10

The single-ended input to differential-ended output amplifier circuit as claimed in claim 1 , wherein the amplifier further comprises a fourth transistor coupled between the first output end and the first terminal of the third transistor, and a gate coupled to the voltage source.

Claim 11

The single-ended input to differential-ended output amplifier circuit as claimed in claim 1 , wherein the amplifier further comprises a bias source to provide a bias to the second node.

Claim 12

The single-ended input to differential-ended output amplifier circuit as claimed in claim 10 , wherein the amplifier further comprises a third resistor coupled between the bias source and the second node.

Claim 13

The single-ended input to differential-ended output amplifier circuit as claimed in claim 1 , wherein the output signal at the second output end and the third output end is a low noise figure and high gain signal.

Claim 14

The single-ended input to differential-ended output amplifier circuit as claimed in claim 1 , wherein the second output end and the third output end is coupled to a first signal input terminal of an image-rejection mixer and a second signal input terminal of the image-rejection mixer, respectively.

Claim 15

The single-ended input to differential-ended output amplifier circuit as claimed in claim 13 , further comprising: a fourth capacitor coupled between the second output end and the first signal input terminal; and a fifth capacitor coupled between the third output end and the second signal input terminal.

Claim 16

A signal processing circuit, comprising: an amplifier for amplifying an input signal into an amplified signal, comprising: an input end for receiving the input signal; and a first output end; a single-ended input to differential-ended output conversion circuit for amplifying the amplified signal into a differential signal pair, comprising: a first transistor for receiving the amplified signal having a gate coupled to the first input end, a first terminal coupled to a second output end, and a second terminal coupled to a first node; a second transistor having a gate, a first terminal coupled to a third output end, and a second terminal coupled to the first node; a first capacitor coupled between the second output end and the gate of the second transistor; a first resistor coupled between the second output end and a voltage source; a second resistor coupled between the third output end and the voltage source; and a current source coupled between the first node and a ground; and an image-rejection mixer, comprising: a first signal input terminal coupled to the second output end; and a second signal input terminal coupled to the third output end, wherein the amplifier further comprises: a first inductor coupled to the input end; a second capacitor coupled between the first inductor and a second node; a second inductor coupled between the voltage source and the first output end; a third transistor having a gate coupled to the second node, a first terminal coupled to the first output end, and a second terminal; and a third inductor coupled between the second terminal of the third transistor and the ground.

Claim 17

A signal processing circuit, comprising: an amplifier for amplifying an input signal into an amplified signal, comprising: an input end for receiving the input signal; and a first output end; a single-ended input to differential-ended output conversion circuit for amplifying the amplified signal into a differential signal pair, comprising: a first transistor for receiving the amplified signal having a gate coupled to the first input end, a first terminal coupled to a second output end, and a second terminal coupled to a first node; a second transistor having a gate, a first terminal coupled to a third output end, and a second terminal coupled to the first node; a first capacitor coupled between the second output end and the gate of the second transistor; a first resistor coupled between the second output end and a voltage source; a second resistor coupled between the third output end and the voltage source; and a current source coupled between the first node and a ground; and an image-rejection mixer, comprising: a first signal input terminal coupled to the second output end; and a second signal input terminal coupled to the third output end, wherein the amplifier further comprises: a first inductor coupled to the input end; a second capacitor coupled between the first inductor and a second node; a second inductor coupled between the voltage source and the first output end; a third transistor having a gate coupled to the second node, a first terminal coupled to the first output end, and a second terminal; and a third inductor coupled between the second terminal of the third transistor and the ground.

Claim 18

The signal processing circuit as claimed in claim 15 , further comprising an antenna for receiving the input signal.

Claim 19

The signal processing circuit as claimed in claim 16 , wherein the antenna is a single-ended antenna.

Claim 20

The signal processing circuit as claimed in claim 15 , wherein the input signal is a radio frequency signal.

Claim 21

The signal processing circuit as claimed in claim 15 , further comprising a third capacitor coupled between the first output end and the single-ended input to differential-ended output conversion circuit.

Claim 22

The signal processing circuit as claimed in claim 15 , wherein the amplifier is a single-ended input to single-ended output amplifier.

Claim 23

The signal processing circuit as claimed in claim 20 , wherein the amplifier is a low noise amplifier.

Claim 24

The signal processing circuit as claimed in claim 21 , wherein the amplifier is a cascade amplifier.

Claim 25

The signal processing circuit as claimed in claim 15 , wherein the amplifier further comprises a fourth transistor coupled between the first output end and the first terminal of the third transistor, and a gate coupled to the voltage source.

Claim 26

The signal processing circuit as claimed in claim 15 , wherein the amplifier further comprises a bias source to provide a bias to the second node.

Claim 27

The signal processing circuit as claimed in claim 24 , wherein the amplifier further comprises a third resistor coupled between the bias source and the second node.

Claim 28

The signal processing circuit as claimed in claim 15 , wherein the output signal at the second output end and the third output end is a low noise figure and high gain signal.

Claim 29

The signal processing circuit as claimed in claim 15 , further comprising: a fourth capacitor coupled between the second output end and the first signal input terminal; and a fifth capacitor coupled between the third output end and the second signal input terminal.