US4885550A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal input to differential output amplifier
Assignee: Motorola Solutions Inc
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Filing: 1988-12-01
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Granted: 1989-12-05
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Expires: 2008-12-01
Abstract
Abstract A single input, differential output amplifier (50) includes two Gallium Arsenide field effect transistors: one arranged to form a common gate amplifier (55) to provide a non-inventing output (60), and the other arranged to form a common source (65) amplifier to provide an inverting output (61). The input of each FET is connected to receive an input signal simultaneously thereby minimizing phase delay in the differential output signals. In another aspect of the invention, the non-inverting stage (55) is incorporated into the biasing network for the inverting ampllifier (65).
Inventors
- 👤 Enrique Ferrer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:39
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/68; H03F3/30; H03F3/3001
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
72 words
A single input, differential output amplifier having reduced phase error, comprising: an inverting stage for driving an independent load including an input port, an output port, and an inverting transistor, a non-inverting stage for driving another independent load, including an input port, an output port, and a non-inverting transistor, said input port of said inverting stage being coupled to said input port of said non-inverting stage for simultaneously receiving an input signal.
Claim 2
Dependent Claim
72 words
A single input, differential output amplifier having reduced phase error, comprising: an inverting stage for driving an independent load including an input port, an output port, and an inverting transistor, a non-inverting stage for driving another independent load, including an input port, an output port, and a non-inverting transistor, said input port of said inverting stage being coupled to said input port of said non-inverting stage for simultaneously receiving an input signal.
Claim 3
Dependent Claim
27 words
A single input, differential output as defined in claim 1, in which said inverting transistor comprises an inverting FET and said non-inverting transistor comprises a non-inverting FET.
Claim 4
Dependent Claim
76 words
A single input, differential output amplifier, comprising: an inverting stage having an input port and an output port, a non-inverting stage having an input port and an output port, said input port of said inverting stage being coupled to said input port of said noninverting stage for simultaneously receiving an input signal, said inverting stage and said non-inverting stage each includes a FET, said FET of said non-inverting stage being arranged in a common gate configuration.
Claim 5
Dependent Claim
76 words
A single input, differential output amplifier, comprising: an inverting stage having an input port and an output port, a non-inverting stage having an input port and an output port, said input port of said inverting stage being coupled to said input port of said noninverting stage for simultaneously receiving an input signal, said inverting stage and said non-inverting stage each includes a FET, said FET of said non-inverting stage being arranged in a common gate configuration.
Claim 6
Dependent Claim
76 words
A single input, differential output amplifier, comprising: an inverting stage having an input port and an output port, a non-inverting stage having an input port and an output port, said input port of said inverting stage being coupled to said input port of said noninverting stage for simultaneously receiving an input signal, said inverting stage and said non-inverting stage each includes a FET, said FET of said inverting stage being arranged in a common source configuration.
Claim 7
Dependent Claim
76 words
A single input, differential output amplifier, comprising: an inverting stage having an input port and an output port, a non-inverting stage having an input port and an output port, said input port of said inverting stage being coupled to said input port of said noninverting stage for simultaneously receiving an input signal, said inverting stage and said non-inverting stage each includes a FET, said FET of said inverting stage being arranged in a common source configuration.
Claim 8
Dependent Claim
90 words
A single input, differential output amplifier, comprising: an inverting stage having an input port and an output port, a non-inverting stage having an input port and an output port, said input port of said inverting stage being coupled to said input port of said noninverting stage for simultaneously receiving an input signal, said inverting stage and said non-inverting stage each includes a FET, said FET of said non-inverting stage being arranged in a common gate configuration, and said FET of said inverting stage being arranged in a common source configuration.
Claim 9
Dependent Claim
90 words
A single input, differential output amplifier, comprising: an inverting stage having an input port and an output port, a non-inverting stage having an input port and an output port, said input port of said inverting stage being coupled to said input port of said noninverting stage for simultaneously receiving an input signal, said inverting stage and said non-inverting stage each includes a FET, said FET of said non-inverting stage being arranged in a common gate configuration, and said FET of said inverting stage being arranged in a common source configuration.
Claim 10
Dependent Claim
69 words
In a single input, differential output amplifier, driving independent loads, a method for reducing phase error comprising the steps of: (a) providing a non-inverting stage having an input port, an output port, and a non-inverting transistor, (b) providing an inverting stage having an input port, an output port, and an inverting transistor, (c) coupling said input port of said non-inverting stage to said input port of said inverting port.
Claim 11
Dependent Claim
69 words
In a single input, differential output amplifier, driving independent loads, a method for reducing phase error comprising the steps of: (a) providing a non-inverting stage having an input port, an output port, and a non-inverting transistor, (b) providing an inverting stage having an input port, an output port, and an inverting transistor, (c) coupling said input port of said non-inverting stage to said input port of said inverting port.
Claim 12
Dependent Claim
29 words
Method of reducing phase error of claim 10, in which step (a) comprises providing an inverting field effect transistor, and step (b) comprises providing a non-inverting field effect transistor.
Claim 13
Dependent Claim
59 words
Method of reducing phase error comprising: (a) providing a common gate field effect transistor non-inverting stage having an input port and an output port, (b) providing a common source field effect transistor inverting stage having an input port and an output port, (c) coupling said input port of said non-inverting stage to said input port of said inverting stage.
Claim 14
Dependent Claim
59 words
Method of reducing phase error comprising: (a) providing a common gate field effect transistor non-inverting stage having an input port and an output port, (b) providing a common source field effect transistor inverting stage having an input port and an output port, (c) coupling said input port of said non-inverting stage to said input port of said inverting stage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-04 | 1993-06-05 | 1993-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-04 | 1997-06-05 | 1997-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-04 | 2001-06-05 | 2001-12-05 | $7700.00 | Window Closed / Lapsed |