US7193475B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single-ended input to differential output low noise amplifier with a cascode topology
Assignee: Richwave Technology Corp
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Filing: 2005-05-09
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Granted: 2007-03-20
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Expires: 2025-05-09
Abstract
Abstract A single-ended input to differential output LNA with a cascode topology of the present invention overcomes a much greater consumption of current and area for the single-ended input to differential output LNA of the prior art. The LNA needs to supply an operating bias for each transistor. The LNA has a few transistors, a few capacitive impedances, and a few inductive impedances. The main objective of the present invention not only reduces costs and conserves area and current consumption, but also has a much higher linearity and gain under the same current consumption when compare to the prior art.
Inventors
- 👤 Jiong-Guang Su
- 👤 Tsyr-Shyang Liou
- 👤 Shyh-Chyi Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:35
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/08; H03F1/22; H03F2200/00; H03F2200/294; H03F2200/372
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
302 words
A single-ended input to differential output LNA with a cascode topology, wherein said LNA needs to supply an operating bias for each transistor, said LNA comprising: a first metal-oxide-semiconductor field effect transistor (MOSFET) and a second MOSFET, for amplifying a signal, the signal being input by and output from a gate terminal, a drain terminal and a source terminal of each said MOSFET; a first capacitive impedance, for serving as a low impedance at high frequencies, wherein one terminal thereof is electrically connected to the drain terminal of said first MOSFET, and another terminal thereof is electrically connected to the gate terminal of said second MOSFET; a first inductive impedance, for serving as a high impedance at high frequencies, wherein one terminal thereof is electrically connected to the drain terminal of said first MOSFET and another terminal thereof is electrically connected to the source terminal of said second MOSFET; a second inductive impedance, for serving as a high impedance at high frequencies, wherein one terminal thereof is electrically connected to the drain terminal of said second MOSFET and another terminal thereof is electrically connected to a first voltage source; a second capacitive impedance, for serving as a low impedance at high frequencies, wherein one terminal thereof is electrically connected to the source terminal of said second MOSFET and another terminal thereof is electrically connected to the ground; and a third inductive impedance, for part of impedance matching at high frequencies, wherein one terminal thereof is electrically connected to the source terminal of said first MOSFET and another terminal thereof is electrically connected to a second voltage source; whereby a high frequency signal is input into the gate terminal of said first MOSFET and then an amplified differential signal is output from the drain terminal of said first MOSFET and said second MOSFET.
Claim 2
Dependent Claim
302 words
A single-ended input to differential output LNA with a cascode topology, wherein said LNA needs to supply an operating bias for each transistor, said LNA comprising: a first metal-oxide-semiconductor field effect transistor (MOSFET) and a second MOSFET, for amplifying a signal, the signal being input by and output from a gate terminal, a drain terminal and a source terminal of each said MOSFET; a first capacitive impedance, for serving as a low impedance at high frequencies, wherein one terminal thereof is electrically connected to the drain terminal of said first MOSFET, and another terminal thereof is electrically connected to the gate terminal of said second MOSFET; a first inductive impedance, for serving as a high impedance at high frequencies, wherein one terminal thereof is electrically connected to the drain terminal of said first MOSFET and another terminal thereof is electrically connected to the source terminal of said second MOSFET; a second inductive impedance, for serving as a high impedance at high frequencies, wherein one terminal thereof is electrically connected to the drain terminal of said second MOSFET and another terminal thereof is electrically connected to a first voltage source; a second capacitive impedance, for serving as a low impedance at high frequencies, wherein one terminal thereof is electrically connected to the source terminal of said second MOSFET and another terminal thereof is electrically connected to the ground; and a third inductive impedance, for part of impedance matching at high frequencies, wherein one terminal thereof is electrically connected to the source terminal of said first MOSFET and another terminal thereof is electrically connected to a second voltage source; whereby a high frequency signal is input into the gate terminal of said first MOSFET and then an amplified differential signal is output from the drain terminal of said first MOSFET and said second MOSFET.
Claim 3
Dependent Claim
28 words
The single-ended input to differential output LNA with a cascode topology as claimed in claim 1 , wherein said first MOSFET and said second MOSFET are N-type MOSFETs.
Claim 4
Dependent Claim
28 words
The single-ended input to differential output LNA with a cascode topology as claimed in claim 1 , wherein said first MOSFET and said second MOSFET are P-type MOSFETs.
Claim 5
Dependent Claim
37 words
The single-ended input to differential output LNA with a cascode topology as claimed in claim 1 , further comprising a bias circuit electrically connected to the gate terminal of said first MOSFET and said second MOSFET, respectively.
Claim 6
Dependent Claim
61 words
The single-ended input to differential output LNA with a cascode topology as claimed in claim 1 , further comprising a DC blocking capacitor electrically connected to the gate terminal of said first MOSFET, for performing a high frequency accessing of said first MOSFET, wherein the operating bias of said first MOSFET is not changed by another impedance of an outside circuit.
Claim 7
Dependent Claim
41 words
The single-ended input to differential output LNA with a cascode topology as claimed in claim 1 , wherein a body voltage of said first MOSFET and said second MOSFET are used as a voltage to satisfy a demand of circuit design.
Claim 8
Dependent Claim
42 words
The single-ended input to differential output LNA with a cascode topology as claimed in claim 1 , wherein the physical layout size of said first MOSFET and said second MOSFET is changed to adjust a required linearity and gain of said LNA.
Claim 9
Dependent Claim
40 words
The single-ended input to differential output LNA with a cascode topology as claimed in claim 1 , wherein the bias of said first MOSFET and said second MOSFET is changed to adjust a required linearity and gain of said LNA.
Claim 10
Dependent Claim
298 words
A single-ended input to differential output LNA with a cascode topology, wherein said LNA supplies an operating bias for each transistor, said LNA comprising: a first bipolar junction transistor (BJT) and a second BJT, for amplifying a signal, the signal input into and output by a base terminal, a collector terminal and an emitter terminal of each said BJT; a first capacitive impedance, for serving as a low impedance at high frequencies, wherein one terminal thereof is electrically connected to the collector terminal of said first BJT and another terminal thereof is electrically connected to the base terminal of said second BJT; a first inductive impedance, for serving as a high impedance at high frequencies, wherein one terminal thereof is electrically connected to the collector terminal of said first BJT and another terminal thereof is electrically connected to the emitter terminal of said second BJT; a second inductive impedance, for serving as a high impedance at high frequencies, wherein one terminal thereof is electrically connected to the collector terminal of said second BJT and another terminal thereof is electrically connected to a first voltage source; a second capacitive impedance, for serving as a low impedance at high frequencies, wherein one terminal thereof is electrically connected to the emitter terminal of said second BJT and another terminal thereof is electrically connected to a ground; and a third inductive impedance, for part of impedance matching at high frequencies, wherein one terminal thereof is electrically connected to the emitter terminal of said first BJT and another terminal thereof is electrically connected to a second voltage source; whereby a high frequency signal is input into the base terminal of said first BJT and then an amplified differential signal is output from the collector terminal of said first BJT and said second BJT.
Claim 11
Dependent Claim
298 words
A single-ended input to differential output LNA with a cascode topology, wherein said LNA supplies an operating bias for each transistor, said LNA comprising: a first bipolar junction transistor (BJT) and a second BJT, for amplifying a signal, the signal input into and output by a base terminal, a collector terminal and an emitter terminal of each said BJT; a first capacitive impedance, for serving as a low impedance at high frequencies, wherein one terminal thereof is electrically connected to the collector terminal of said first BJT and another terminal thereof is electrically connected to the base terminal of said second BJT; a first inductive impedance, for serving as a high impedance at high frequencies, wherein one terminal thereof is electrically connected to the collector terminal of said first BJT and another terminal thereof is electrically connected to the emitter terminal of said second BJT; a second inductive impedance, for serving as a high impedance at high frequencies, wherein one terminal thereof is electrically connected to the collector terminal of said second BJT and another terminal thereof is electrically connected to a first voltage source; a second capacitive impedance, for serving as a low impedance at high frequencies, wherein one terminal thereof is electrically connected to the emitter terminal of said second BJT and another terminal thereof is electrically connected to a ground; and a third inductive impedance, for part of impedance matching at high frequencies, wherein one terminal thereof is electrically connected to the emitter terminal of said first BJT and another terminal thereof is electrically connected to a second voltage source; whereby a high frequency signal is input into the base terminal of said first BJT and then an amplified differential signal is output from the collector terminal of said first BJT and said second BJT.
Claim 12
Dependent Claim
28 words
The single-ended input to differential output LNA with a cascode topology as claimed in claim 1 , wherein said first BJT and said second BJT are NPN-type BJTs.
Claim 13
Dependent Claim
28 words
The single-ended input to differential output LNA with a cascode topology as claimed in claim 1 , wherein said first BJT and said second BJT are PNP-type BJTs.
Claim 14
Dependent Claim
37 words
The single-ended input to differential output LNA with a cascode topology as claimed in claim 1 , further comprising a bias circuit electrically connected to the base terminal of said first BJT and said second BJT, respectively.
Claim 15
Dependent Claim
61 words
The single-ended input to differential output LNA with a cascode topology as claimed in claim 1 , further comprising a DC blocking capacitor electrically connected to the base terminal of said first BJT, for performing a high frequency accessing of said first BJT, wherein the operating bias of said first BJT is not changed by another impedance of an outside circuit.
Claim 16
Dependent Claim
40 words
The single-ended input to differential output LNA with a cascode topology as claimed in claim 1 , wherein a substrate voltage of said first BJT and said second BJT is used as a voltage to satisfy a circuit design requirement.
Claim 17
Dependent Claim
42 words
The single-ended input to differential output LNA with a cascode topology as claimed in claim 1 , wherein the physical layout size of said first BJT and said second BJT is changed to adjust a required linearity and gain of said LNA.
Claim 18
Dependent Claim
40 words
The single-ended input to differential output LNA with a cascode topology as claimed in claim 1 , wherein the bias of said first BJT and said second BJT is changed to adjust a required linearity and gain of said LNA.
References Cited (Backward Citations)
US5868061A
Cited
US6094108A
Cited
US6133793A
Cited
US6122532A
Cited
US7035616B2
Cited
US6850120B2
Cited
US7053718B2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-03-19 | 2010-09-18 | 2011-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-03-19 | 2014-09-18 | 2015-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-03-19 | 2018-09-18 | 2019-03-20 | $7700.00 | Window Closed / Lapsed |