Patent US7276799B2 successfully refreshed from Google Patents.
US7276799B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Chip stack package and manufacturing method thereof
Assignee: Samsung Electronics Co Ltd
•
Filing: 2004-07-15
•
Granted: 2007-10-02
•
Expires: 2024-07-15
Abstract
Abstract A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.
Inventors
- 👤 Kang-Wook Lee
- 👤 Gu-Sung Kim
- 👤 Dong-Hyeon Jang
- 👤 Seung-Duk Baek
- 👤 Jae-Sik Chung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:05
CPC Classifications
H; H10; H10W; H10W72/00; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W20/0245; H10W20/20; H10W70/00; H10W70/099; H10W90/00; H10W70/60; H10W70/611; H10W70/614; H10W70/62; H10W70/65; H10W70/654; H10W70/655; H10W72/01; H10W72/012; H10W72/019; H10W72/0198; H10W72/071; H10W72/072; H10W72/07251; H10W72/07254; H10W72/20; H10W72/221; H10W72/241; H10W72/244; H10W72/247; H10W72/50; H10W72/531; H10W72/5366; H10W72/851; H10W72/874; H10W72/884; H10W72/90; H10W72/921; H10W72/922; H10W72/9223; H10W72/923; H10W72/931; H10W72/934; H10W72/941; H10W72/9415; H10W72/942; H10W72/944; H10W72/951; H10W72/952; H10W74/00; H10W74/10; H10W74/131; H10W74/142; H10W90/20; H10W90/291; H10W90/297; H10W90/701; H10W90/721; H10W90/722; H10W90/724; H10W90/731; H10W90/732; H10W90/734; H10W90/751; H10W90/754; Y; Y02; Y02P; Y02P80/00; Y02P80/30; Y10; Y10S; Y10S438/00; Y10S438/977; Y10T; Y10T436/00; Y10T436/10; Y10T436/104998; Y10T436/108331; Y10T436/17; Y10T436/173845; Y10T436/175383
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
248 words
A chip stack package comprising: a substrate, the substrate including a first surface, the first surface including a plurality of substrate terminals, and a second surface, the second surface including a plurality of connection terminals, the connection terminals being in electrical contact with the substrate terminals; a first chip, the first chip including a backside surface, an active surface, the active surface having a device periphery, a residual portion of a scribe lane extending outwardly from the device periphery of the active surface, a plurality of first connection vias formed through the residual portion of the scribe lane, the first connection vias having an upper surface and a lower surface, the first chip being disposed on and electrically connected to the first surface of the substrate, the electrical connection being established between the lower surfaces of the first connection vias and the substrate terminals; a second chip, the second chip including a backside surface, an active surface, the active surface having a device periphery, a residual portion of a scribe lane extending outwardly from the device periphery of the active surface, a plurality of second connection vias formed through the residual portion of the scribe lane, the second connection vias having an upper surface and a lower surface, the second chip being disposed on and electrically connected to the active surface of the first chip, the electrical connection being established between the lower surfaces of the second connection vias and the upper surfaces of the first connection vias.
Claim 2
Dependent Claim
248 words
A chip stack package comprising: a substrate, the substrate including a first surface, the first surface including a plurality of substrate terminals, and a second surface, the second surface including a plurality of connection terminals, the connection terminals being in electrical contact with the substrate terminals; a first chip, the first chip including a backside surface, an active surface, the active surface having a device periphery, a residual portion of a scribe lane extending outwardly from the device periphery of the active surface, a plurality of first connection vias formed through the residual portion of the scribe lane, the first connection vias having an upper surface and a lower surface, the first chip being disposed on and electrically connected to the first surface of the substrate, the electrical connection being established between the lower surfaces of the first connection vias and the substrate terminals; a second chip, the second chip including a backside surface, an active surface, the active surface having a device periphery, a residual portion of a scribe lane extending outwardly from the device periphery of the active surface, a plurality of second connection vias formed through the residual portion of the scribe lane, the second connection vias having an upper surface and a lower surface, the second chip being disposed on and electrically connected to the active surface of the first chip, the electrical connection being established between the lower surfaces of the second connection vias and the upper surfaces of the first connection vias.
Claim 3
Dependent Claim
36 words
A chip stack package according to claim 1 , further comprising: a plurality of first connection bumps, the first connection bumps being arranged between the lower surfaces of the first connection vias and the substrate terminals.
Claim 4
Dependent Claim
41 words
A chip stack package according to claim 2 , further comprising: a plurality of second connection bumps, the second connection bumps being arranged between the lower surfaces of the second connection vias and the upper surfaces of the first connection vias.
Claim 5
Dependent Claim
57 words
A chip stack package according to claim 3 , wherein: the first connection bumps are formed from a first conductive material having a melting temperature T 1 and the second connection bumps are formed from a second conductive material having a melting temperature T 2 , and further wherein the relationship T 1 >T 2 is satisfied.
Claim 6
Dependent Claim
19 words
A chip stack package according to claim 1 , wherein: the substrate is a portion of a test wafer.
Claim 7
Dependent Claim
54 words
A chip stack package according to claim 1 , wherein: each of the first and the second chips further includes a plurality of chip pads formed on the active surface and within the device periphery and a plurality of rerouting lines crossing the device periphery for connecting the chip pads to the connection vias.
Claim 8
Dependent Claim
46 words
A chip stack package according to claim 1 , wherein: the lower surfaces of the first connection vias are connected directly to the substrate terminals; and the lower surfaces of the second connection vias are connected directly to the upper surfaces of the first connection vias.
Claim 9
Dependent Claim
20 words
A chip stack package according to claim 3 , wherein: the first and second connection bumps are micro metal bumps.
Claim 10
Dependent Claim
36 words
A chip stack package according to claim 1 , wherein: each of the first and the second connection vias is separated from electrical contact with the residual portion of the scribe lane by an insulating layer.
Claim 11
Dependent Claim
24 words
A chip stack package according to claim 1 , wherein: the first and the second chips are memory chips and have substantially identical dimensions.
References Cited (Backward Citations)
US5032896A
Cited
US5688721A
Cited
US6235554B1
Cited
JPH10223833A
Cited
US5998292A
Cited
US6064114A
Cited
US6391685B1
Cited
KR20000067291A
Cited
US6429509B1
Cited
KR20010001159A
Cited
KR20010018694A
Cited
JP2001093869A
Cited
JP2001223469A
Cited
JP2001210782A
Cited
KR20020012061A
Cited
JP2002170904A
Cited
US6766998B2
Cited
KR20030023040A
Cited
US6734084B1
Cited
US7074703B2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-10-01 | 2011-04-02 | 2011-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-10-01 | 2015-04-02 | 2015-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-10-01 | 2019-04-02 | 2019-10-02 | $7700.00 | Window Closed / Lapsed |