US7266801B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Design pattern correction method and mask pattern producing method
Assignee: Kioxia Corp
•
Filing: 2004-12-16
•
Granted: 2007-09-04
•
Expires: 2024-12-16
Abstract
Abstract There is disclosed a method of correcting a design pattern considering a process margin between layers of a semiconductor integrated circuit, including calculating a first pattern shape corresponding to a processed pattern shape of a first layer based on a first design pattern, calculating a second pattern shape corresponding to a processed pattern shape of a second layer based on a second design pattern, calculating a third pattern shape using a Boolean operation between the first and second pattern shapes, determining whether or not an evaluation value obtained from the third pattern shape satisfies a predetermined value, and correcting at least one of the first and second design patterns if it is determined that the evaluation value does not satisfy the predetermined value.
Inventors
- 👤 Toshiya Kotani
- 👤 Suigen Kyoh
- 👤 Hirotaka Ichikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 17:47
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
116 words
A method of correcting a design pattern considering a process margin between layers of a semiconductor integrated circuit, comprising: calculating a first pattern shape corresponding to a processed pattern shape of a first layer based on a first design pattern; calculating a second pattern shape corresponding to a processed pattern shape of a second layer based on a second design pattern; calculating a third pattern shape from the first and second pattern shapes; determining whether or not an evaluation value obtained from the third pattern shape satisfies a predetermined value; and correcting at least one of the first and second design patterns if it is determined that the evaluation value does not satisfy the predetermined value.
Claim 2
Independent Claim
116 words
A method of correcting a design pattern considering a process margin between layers of a semiconductor integrated circuit, comprising: calculating a first pattern shape corresponding to a processed pattern shape of a first layer based on a first design pattern; calculating a second pattern shape corresponding to a processed pattern shape of a second layer based on a second design pattern; calculating a third pattern shape from the first and second pattern shapes; determining whether or not an evaluation value obtained from the third pattern shape satisfies a predetermined value; and correcting at least one of the first and second design patterns if it is determined that the evaluation value does not satisfy the predetermined value.
Claim 3
Dependent Claim
31 words
The method according to claim 1 , wherein the first pattern shape is calculated from a mask pattern obtained by subjecting the first design pattern to resizing including optical proximity correction.
Claim 4
Dependent Claim
31 words
The method according to claim 1 , wherein the second pattern shape is calculated from a mask pattern obtained by subjecting the second design pattern to resizing including optical proximity correction.
Claim 5
Dependent Claim
28 words
The method according to claim 1 , wherein the evaluation value includes at least one of area, peripheral line length and pattern width of the third pattern shape.
Claim 6
Dependent Claim
81 words
The method according to claim 1 , wherein at lease one of the first and second pattern shapes is calculated considering a predetermined process condition, and the predetermined process condition includes at least one of illumination light wavelength of exposure system, numerical aperture of a lens of the exposure system, illumination shape thereof, focal position thereof, aberration of lens thereof, exposure dose on wafer by the exposure system, alignment error amount, mask dimension and diffusion length of acid contained in resist.
Claim 7
Dependent Claim
32 words
The method according to claim 1 , wherein the first and second layers each correspond to one of gate layer, interconnect layer, contact layer, diffusion layer, ion implantation layer and well layer.
Claim 8
Dependent Claim
37 words
The method according to claim 1 , wherein procedures from calculating the first pattern shape to correcting at least one of the first and second design patterns are repeated until the evaluation value satisfies the predetermined value.
Claim 9
Dependent Claim
28 words
A method of manufacturing a mask comprising: forming a mask pattern based on a design pattern corrected by the method according to claim 1 on a mask substrate.
Claim 10
Dependent Claim
27 words
A method of manufacturing a semiconductor device, comprising: projecting the mask pattern obtained by the method according to claim 8 to a photo resist on a wafer.
Claim 11
Dependent Claim
30 words
The method according to claim 1 , wherein calculating the third pattern shape includes calculating the third pattern shape using a Boolean operation between the first and second pattern shapes.
Claim 12
Dependent Claim
29 words
The method according to claim 10 , wherein the Boolean operation is carried out after at least one of the first and second pattern shapes is moved or resized.
Claim 13
Dependent Claim
24 words
The method according to claim 10 , wherein the Boolean operation is carried out considering an alignment error between the first and second layers.
Claim 14
Dependent Claim
28 words
The method according to claim 10 , wherein the Boolean operation is carried out considering a probability distribution of an alignment error between the first and second layers.
Claim 15
Dependent Claim
23 words
The method according to claim 10 , wherein the Boolean operation includes at least one of an AND operation and a NOT operation.
Claim 16
Independent Claim
154 words
A method of producing a mask pattern considering a process margin between layers of a semiconductor integrated circuit, comprising: resizing a fist design pattern of a first layer at least one time to produce a first mask pattern; resizing a second design pattern of a second layer at least one time to produce a second mask pattern; calculating a first pattern shape corresponding to a processed pattern shape of the first layer based on the first mask pattern; calculating a second pattern shape corresponding to a processed pattern shape of the second layer based on the second mask pattern; calculating a third pattern shape from the first and second pattern shapes; determining whether or not an evaluation value obtained from the third pattern shape satisfies a predetermined value; and correcting at least one of the first and second mask patterns if it is determined that the evaluation vale does not satisfy the predetermined value.
Claim 17
Independent Claim
154 words
A method of producing a mask pattern considering a process margin between layers of a semiconductor integrated circuit, comprising: resizing a fist design pattern of a first layer at least one time to produce a first mask pattern; resizing a second design pattern of a second layer at least one time to produce a second mask pattern; calculating a first pattern shape corresponding to a processed pattern shape of the first layer based on the first mask pattern; calculating a second pattern shape corresponding to a processed pattern shape of the second layer based on the second mask pattern; calculating a third pattern shape from the first and second pattern shapes; determining whether or not an evaluation value obtained from the third pattern shape satisfies a predetermined value; and correcting at least one of the first and second mask patterns if it is determined that the evaluation vale does not satisfy the predetermined value.
Claim 18
Dependent Claim
30 words
The method according to claim 15 , wherein calculating the third pattern shape includes calculating the third pattern shape using a Boolean operation between the first and second pattern shapes.
Claim 19
Independent Claim
134 words
A system of correcting a design pattern considering a process margin between layers of a semiconductor integrated circuit, comprising: a first calculating part calculating a first pattern shape corresponding to a processed pattern shape of a first layer based on a first design pattern; a second calculating part calculating a second pattern shape corresponding to a processed pattern shape of a second layer based on a second design pattern; a third calculating part calculating a third pattern shape from the first and second pattern shapes; a determining part determining whether or not an evaluation value obtained from the third pattern shape satisfies a predetermined value; and a correcting part correcting at least one of the first and second design patterns if it is determined that the evaluation value does not satisfy the predetermined value.
Claim 20
Independent Claim
134 words
A system of correcting a design pattern considering a process margin between layers of a semiconductor integrated circuit, comprising: a first calculating part calculating a first pattern shape corresponding to a processed pattern shape of a first layer based on a first design pattern; a second calculating part calculating a second pattern shape corresponding to a processed pattern shape of a second layer based on a second design pattern; a third calculating part calculating a third pattern shape from the first and second pattern shapes; a determining part determining whether or not an evaluation value obtained from the third pattern shape satisfies a predetermined value; and a correcting part correcting at least one of the first and second design patterns if it is determined that the evaluation value does not satisfy the predetermined value.
Claim 21
Dependent Claim
28 words
The system according to claim 17 , wherein the third calculating part calculates the third pattern shape using a Boolean operation between the first and second pattern shapes.
Claim 22
Dependent Claim
146 words
A computer readable medium configured to store program instructions applied to correcting a design pattern considering a process margin between layers of a semiconductor integrated circuit, the program instructions causing a computer to calculate a first pattern shape corresponding to a processed pattern shape of a first layer based on a first design pattern; causing a computer to calculate a second pattern shape corresponding to a processed pattern shape of a second layer based on a second design pattern; causing a computer to calculate a third pattern shape from the first and second pattern shapes; causing a computer to determine whether or not an evaluation value obtained from the third pattern shape satisfies a predetermined value; and causing a computer to correct at least one of the first and second design patterns if it is determined that the evaluation value does not satisfy the predetermined value.
Claim 23
Dependent Claim
146 words
A computer readable medium configured to store program instructions applied to correcting a design pattern considering a process margin between layers of a semiconductor integrated circuit, the program instructions causing a computer to calculate a first pattern shape corresponding to a processed pattern shape of a first layer based on a first design pattern; causing a computer to calculate a second pattern shape corresponding to a processed pattern shape of a second layer based on a second design pattern; causing a computer to calculate a third pattern shape from the first and second pattern shapes; causing a computer to determine whether or not an evaluation value obtained from the third pattern shape satisfies a predetermined value; and causing a computer to correct at least one of the first and second design patterns if it is determined that the evaluation value does not satisfy the predetermined value.
Claim 24
Dependent Claim
40 words
The computer readable medium according to claim 19 , wherein causing a computer to calculate the third pattern shape includes causing a computer to calculate the third pattern shape using a Boolean operation between the first and second pattern shapes.
References Cited (Backward Citations)
US5677092A
Cited
US6470489B1
Cited
US6316163B1
Cited
US6576147B2
Cited
US6415421B2
Cited
US6507931B2
Cited
JP2002026126A
Cited
US7120882B2
Cited
US6745372B2
Cited
JP2003303742A
Cited
US6949320B2
Cited
US20050085085A1
Cited
US20050088633A1
Cited
US20060051680A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-09-03 | 2011-03-05 | 2011-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-09-03 | 2015-03-05 | 2015-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-09-03 | 2019-03-05 | 2019-09-04 | $7700.00 | Window Closed / Lapsed |