Process for fabricating phase shift mask and process of semiconductor integrated circuit device

Claim 2

A process for fabricating a semiconductor integrated circuit device, comprising the steps of: (a) preparing mask pattern data, for making a phase shift mask, having at least (1) real pattern data corresponding to light-transmissive regions of the mask which lead to actual patterns on an integrated circuit wafer, and (2) phase shift pattern data corresponding to at least one phase shifter of the mask; (b) verifying the phase shift pattern data by using the mask pattern data to inspect whether or not each phase inverted light-transmissive region, of the light-transmissive regions, has a phase shifter extending over an entirety thereof; (c) in accordance with results of the step of verifying, correcting the phase shift pattern data, so as to form corrected phase shift pattern data; (d) forming said at least one phase shifter on a mask substrate on the basis of said corrected phase shift pattern data; and (e) transferring by reduction projection exposure a semiconductor integrated circuit pattern to a resist film on a surface of the wafer, using said phase shift mask.

Claim 3

A process for fabricating a semiconductor integrated circuit device according to claim 1, wherein the steps of preparing, verifying and correcting are each performed by electronic data processing, and the step of forming said at least one phase shifter on the mask substrate is performed by an electron beam exposure method.

Claim 4

A process for fabricating a semiconductor integrated circuit device, which process is performed on a basis of design rules including a minimum line width rule, comprising the steps of: (a) preparing mask pattern data, for making a phase shift mask, having at least real pattern data corresponding to light-transmissive regions of the mask which lead to actual patterns on an integrated circuit wafer, the light-transmissive regions including first light-transmissive regions which have other light-transmissive regions at most neighboring at one side thereof; (b) verifying the real pattern data corresponding to at least one first light-transmissive region, where phases are inverted, to inspect whether or not the width of each first light-transmissive region is no less than a value substantially larger than the minimum line width defined by the design rule corresponding to phase alternating line and space patterns on the wafer; (c) in accordance with results of the step of verifying, correcting the real pattern data, so as to form corrected real pattern data; (d) forming said light-transmissive regions on a mask substrate, on the basis of said corrected real pattern data; and (e) transferring by reduction projection exposure a semiconductor integrated circuit pattern to a resist film on a surface of the wafer, using said phase shift mask.

Claim 5

A process for fabricating a semiconductor integrated circuit device, which process is performed on a basis of design rules including a minimum line width rule, comprising the steps of: (a) preparing mask pattern data, for making a phase shift mask, having at least real pattern data corresponding to light-transmissive regions of the mask which lead to actual patterns on an integrated circuit wafer, the light-transmissive regions including first light-transmissive regions which have other light-transmissive regions at most neighboring at one side thereof; (b) verifying the real pattern data corresponding to at least one first light-transmissive region, where phases are inverted, to inspect whether or not the width of each first light-transmissive region is no less than a value substantially larger than the minimum line width defined by the design rule corresponding to phase alternating line and space patterns on the wafer; (c) in accordance with results of the step of verifying, correcting the real pattern data, so as to form corrected real pattern data; (d) forming said light-transmissive regions on a mask substrate, on the basis of said corrected real pattern data; and (e) transferring by reduction projection exposure a semiconductor integrated circuit pattern to a resist film on a surface of the wafer, using said phase shift mask.

Claim 6

A process for fabricating a semiconductor integrated circuit device according to claim 3, wherein the steps of preparing, verifying and correcting are each performed by electronic data processing, and the step of forming the light-transmissive regions on the mask substrate is performed by an electron beam exposure method.

Claim 7

A process for fabricating a semiconductor integrated circuit device, which process is performed on a basis of design rules including a minimum line width rule, comprising the steps of: (a) preparing mask pattern data, for making a phase shift mask, having at least real pattern data corresponding to light-transmissive regions of the mask which lead to actual patterns on an integrated circuit wafer; (b) verifying the real pattern data corresponding to line and space patterns, disposed adjacent each other on the wafer, having substantially a same phase on the mask, to inspect whether or not the width of each of the line and space patterns is no less than a value substantially larger than the minimum line width defined by a design rule corresponding to phase alternating line and space patterns on the wafer; (c) in accordance with results of the step of verifying, correcting real pattern data, so as to form corrected real pattern data; (d) forming the light-transmissive regions on a mask substrate on the basis of said corrected real pattern data; and (e) transferring by reduction projection exposure a semiconductor integrated circuit pattern to a resist film on a surface of the wafer, using said phase shift mask.

Claim 8

A process for fabricating a semiconductor integrated circuit device, which process is performed on a basis of design rules including a minimum line width rule, comprising the steps of: (a) preparing mask pattern data, for making a phase shift mask, having at least real pattern data corresponding to light-transmissive regions of the mask which lead to actual patterns on an integrated circuit wafer; (b) verifying the real pattern data corresponding to line and space patterns, disposed adjacent each other on the wafer, having substantially a same phase on the mask, to inspect whether or not the width of each of the line and space patterns is no less than a value substantially larger than the minimum line width defined by a design rule corresponding to phase alternating line and space patterns on the wafer; (c) in accordance with results of the step of verifying, correcting real pattern data, so as to form corrected real pattern data; (d) forming the light-transmissive regions on a mask substrate on the basis of said corrected real pattern data; and (e) transferring by reduction projection exposure a semiconductor integrated circuit pattern to a resist film on a surface of the wafer, using said phase shift mask.

Claim 9

A process for fabricating a semiconductor integrated circuit device according to claim 5, wherein the steps of preparing, verifying and correcting are each performed by electronic data processing, and the step of forming the light-transmissive regions on the mask substrate is performed by an electron beam exposure method.

Claim 10

A process for fabricating a semiconductor integrated circuit device, comprising the steps of: (a) preparing mask pattern data, for making a phase shift mask, having at least real pattern data corresponding to light-transmissive regions of the mask which lead to actual patterns on an integrated circuit wafer; (b) verifying whether or not a gap between each adjacent pair of light-transmissive regions having phase shift patterns arranged thereon and light-transmissive regions without said phase shift patterns on the mask is no more than a specific value, using said mask pattern data of said phase shift mask; (c) in accordance with results of the step of verifying, correcting the real pattern data, so as to form corrected real pattern data; (d) forming the light-transmissive regions on a mask substrate on the basis of said corrected real pattern data; and (e) transferring by reduction projection exposure a semiconductor integrated circuit pattern to a resist film on a surface of the wafer, using said phase shift mask.

Claim 11

A process for fabricating a semiconductor integrated circuit device, comprising the steps of: (a) preparing mask pattern data, for making a phase shift mask, having at least real pattern data corresponding to light-transmissive regions of the mask which lead to actual patterns on an integrated circuit wafer; (b) verifying whether or not a gap between each adjacent pair of light-transmissive regions having phase shift patterns arranged thereon and light-transmissive regions without said phase shift patterns on the mask is no more than a specific value, using said mask pattern data of said phase shift mask; (c) in accordance with results of the step of verifying, correcting the real pattern data, so as to form corrected real pattern data; (d) forming the light-transmissive regions on a mask substrate on the basis of said corrected real pattern data; and (e) transferring by reduction projection exposure a semiconductor integrated circuit pattern to a resist film on a surface of the wafer, using said phase shift mask.

Claim 12

A process for fabricating a semiconductor integrated circuit device according to claim 7, wherein the steps of preparing and verifying are performed by electronic data processing, and the step of forming the light-transmissive regions on the mask is performed by an electron beam exposure method.