US6745372B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for facilitating process-compliant layout optimization
Assignee: Synopsys Inc
•
Filing: 2002-04-05
•
Granted: 2004-06-01
•
Expires: 2022-04-05
Abstract
Abstract One embodiment of the invention provides a system that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size. During operation, the system receives a representation of a target layout for the integrated circuit, wherein the representation defines a plurality of shapes that comprise the target layout. Next, the system simulates effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout. The system then identifies problem areas in the simulated printed image that do not meet a specification. Next, the system moves corresponding shapes in the target layout to produce a new target layout for the integrated circuit, so that a simulated printed image of the new target layout meets the specification.
Inventors
- 👤 Michel Luc Côté
- 👤 Philippe Hurat
- 👤 Christophe Pierrat
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 02:31
CPC Classifications
G; G03; G03F; G03F1/00; G03F1/36; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F2119/00; G06F2119/18; Y; Y02; Y02P; Y02P90/00; Y02P90/02
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
167 words
A method for simulating effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, comprising: receiving a representation of a target layout for the integrated circuit, wherein the representation defines a plurality of shapes that comprise the target layout; simulating effects of a manufacturing process on the target layout to produce a simulated printed image for the target layout; identifying problem areas in the simulated printed image that do not meet a specification; and moving corresponding shapes in the target layout to produce new target layout for the integrated circuit, wherein moving the corresponding shapes in the target layout involves applying relaxed rules to the problem areas of the target layout to achieve an enhanced process latitude regardless of the area impact and applying standard design rules on remaining areas of the target layout, wherein the relaxed rules include priority values for resolving conflicts between relaxed rules whereby a simulated printed image of the new target layout meets the specification.
Claim 2
Independent Claim
167 words
A method for simulating effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, comprising: receiving a representation of a target layout for the integrated circuit, wherein the representation defines a plurality of shapes that comprise the target layout; simulating effects of a manufacturing process on the target layout to produce a simulated printed image for the target layout; identifying problem areas in the simulated printed image that do not meet a specification; and moving corresponding shapes in the target layout to produce new target layout for the integrated circuit, wherein moving the corresponding shapes in the target layout involves applying relaxed rules to the problem areas of the target layout to achieve an enhanced process latitude regardless of the area impact and applying standard design rules on remaining areas of the target layout, wherein the relaxed rules include priority values for resolving conflicts between relaxed rules whereby a simulated printed image of the new target layout meets the specification.
Claim 3
Dependent Claim
48 words
The method of claim 1 , further comprising performing optical proximity correction (OPC) on the new target layout to produce a modified layout, wherein a simulated printed image of modified layout more closely matches the new target layout than the simulated printed image of the new target layout.
Claim 4
Dependent Claim
19 words
The method of claim 1 , wherein moving the corresponding shapes in the target layout involves optimizing process latitude.
Claim 5
Dependent Claim
24 words
The method of claim 1 , wherein moving the corresponding shapes in the target layout involves performing a compaction process to minimize layout size.
Claim 6
Dependent Claim
28 words
The method of claim 4 , wherein moving the corresponding shapes in the target layout involves providing at least one of objectives and constraints to the compaction process.
Claim 7
Dependent Claim
21 words
The method of claim 1 , wherein the effects of the manufacturing process are simulated over a range of manufacturing parameters.
Claim 8
Dependent Claim
24 words
The method of claim 1 , wherein the method further comprises using the simulated printed image to estimate a yield for the target layout.
Claim 9
Dependent Claim
26 words
The method of claim 1 , further comprising using information obtained from examining the simulated printed image to formulate new design rules for the target layout.
Claim 10
Dependent Claim
25 words
The method of claim 1 , wherein the target layout defines a standard cell that is used as a building block for the integrated circuit.
Claim 11
Dependent Claim
27 words
The method of claim 1 , further comprising performing a design rule checking operation on the target layout prior to simulating the effects of the manufacturing process.
Claim 12
Dependent Claim
186 words
A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for simulating effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, the method comprising: receiving a representation of a target layout for the integrated circuit; wherein the representation defines a plurality of shapes that comprise the target layout; simulating effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout; identifying problem areas in the simulated printed image that do not meet a specification; and moving corresponding shapes in the target layout to produce new target layout for the integrated circuit, wherein moving the corresponding shapes in the target layout involves applying relaxed rules to the problem areas of the target layout to achieve an enhanced process latitude regardless of the area impact and applying standard design rules on remaining areas of the target layout, wherein the relaxed rules include priority values for resolving conflicts between relaxed rules whereby a simulated printed image of the new target layout meets the specification.
Claim 13
Dependent Claim
186 words
A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for simulating effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, the method comprising: receiving a representation of a target layout for the integrated circuit; wherein the representation defines a plurality of shapes that comprise the target layout; simulating effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout; identifying problem areas in the simulated printed image that do not meet a specification; and moving corresponding shapes in the target layout to produce new target layout for the integrated circuit, wherein moving the corresponding shapes in the target layout involves applying relaxed rules to the problem areas of the target layout to achieve an enhanced process latitude regardless of the area impact and applying standard design rules on remaining areas of the target layout, wherein the relaxed rules include priority values for resolving conflicts between relaxed rules whereby a simulated printed image of the new target layout meets the specification.
Claim 14
Dependent Claim
53 words
The computer-readable storage medium of claim 11 , wherein the method further comprises performing optical proximity correction (OPC) on the new target layout to produce a modified layout, wherein a simulated printed image of modified layout more closely matches the new target layout than the simulated printed image of the new target layout.
Claim 15
Dependent Claim
25 words
The computer-readable storage medium of claim 11 , wherein moving the corresponding shapes in the target layout involves optimizing process latitude for the target layout.
Claim 16
Dependent Claim
26 words
The computer-readable storage medium of claim 11 , wherein moving the corresponding shapes in the target layout involves performing a compaction process to minimize layout size.
Claim 17
Dependent Claim
30 words
The computer-readable storage medium of claim 14 , wherein moving the corresponding shapes in the target layout involves providing at least one of objectives and constraints to the compaction process.
Claim 18
Dependent Claim
23 words
The computer-readable storage medium of claim 11 , wherein the effects of the manufacturing process are simulated over a range of manufacturing parameters.
Claim 19
Dependent Claim
26 words
The computer-readable storage medium of claim 11 , wherein the method further comprises using the simulated printed image to estimate a yield for the target layout.
Claim 20
Dependent Claim
31 words
The computer-readable storage medium of claim 11 , wherein the method further comprises using information obtained from examining the simulated printed image to formulate new design rules for the target layout.
Claim 21
Dependent Claim
27 words
The computer-readable storage medium of claim 11 , wherein the target layout defines a standard cell that is used as a building block for the integrated circuit.
Claim 22
Dependent Claim
32 words
The computer-readable storage medium of claim 11 , wherein the method further comprises performing a design rule checking operation on the target layout prior to simulating the effects of the manufacturing process.
Claim 23
Independent Claim
190 words
An apparatus for simulating effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, comprising: a receiving mechanism that is configured to receive a representation of a target layout for the integrated circuit; wherein the representation defines a plurality of shapes that comprise the target layout; a simulation mechanism that is configured to simulate effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout; and an optimization mechanism that is configured to, identify problem areas in the simulated printed image that do not meet a specification, and to move corresponding shapes in the target layout to produce new target layout for the integrated circuit, wherein moving the corresponding shapes in the target layout involves applying relaxed rules to the problem areas of the target layout to achieve an enhanced process latitude regardless of the area impact and applying standard design rules on remaining areas of the target layout, wherein the relaxed rules include priority values for resolving conflicts between relaxed rules whereby a simulated printed image of the new target layout meets the specification.
Claim 24
Independent Claim
190 words
An apparatus for simulating effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, comprising: a receiving mechanism that is configured to receive a representation of a target layout for the integrated circuit; wherein the representation defines a plurality of shapes that comprise the target layout; a simulation mechanism that is configured to simulate effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout; and an optimization mechanism that is configured to, identify problem areas in the simulated printed image that do not meet a specification, and to move corresponding shapes in the target layout to produce new target layout for the integrated circuit, wherein moving the corresponding shapes in the target layout involves applying relaxed rules to the problem areas of the target layout to achieve an enhanced process latitude regardless of the area impact and applying standard design rules on remaining areas of the target layout, wherein the relaxed rules include priority values for resolving conflicts between relaxed rules whereby a simulated printed image of the new target layout meets the specification.
Claim 25
Dependent Claim
55 words
The apparatus of claim 21 , further comprising an optical proximity correction (OPC) mechanism that is configured to perform OPC on the new target layout to produce a modified layout, wherein a simulated printed image of modified layout more closely matches the new target layout than the simulated printed image of the new target layout.
Claim 26
Dependent Claim
20 words
The apparatus of claim 21 , wherein the optimization mechanism is configured to optimize process latitude for the target layout.
Claim 27
Dependent Claim
21 words
The apparatus of claim 21 , wherein the optimization mechanism is configured to perform a compaction process to minimize layout size.
Claim 28
Dependent Claim
34 words
The apparatus of claim 24 , wherein the optimization mechanism is configured to move the corresponding shapes in the target layout by providing at least one of objectives and constraints to the compaction process.
Claim 29
Dependent Claim
25 words
The apparatus of claim 21 , wherein the simulation mechanism is configured to simulate effects of the manufacturing process over a range of manufacturing parameters.
Claim 30
Dependent Claim
21 words
The apparatus of claim 21 , wherein the optimization mechanism is additionally configured to estimate a yield for the target layout.
Claim 31
Dependent Claim
31 words
The apparatus of claim 21 , wherein the optimization mechanism is configured to use information obtained from examining the simulated printed image to formulate new design rules for the target layout.
Claim 32
Dependent Claim
25 words
The apparatus of claim 21 , wherein the target layout defines a standard cell that is used as a building block for the integrated circuit.
Claim 33
Dependent Claim
36 words
The apparatus of claim 21 , further comprising a design rule checking mechanism that is configured to perform a design rule checking operation on the target layout prior feeding the target layout to the simulation mechanism.
Claim 34
Dependent Claim
185 words
A mask to be used in an optical lithography process, wherein the mask is created through a method that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, the method comprising: receiving a representation of a target layout for the integrated circuit; wherein the representation defines a plurality of shapes that comprise the target layout; simulating effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout; identifying problem areas in the simulated printed image that do not meet a specification; and moving corresponding shapes in the target layout to produce new target layout for the integrated circuit, wherein moving the corresponding shapes in the target layout involves applying relaxed rules to the problem areas of the target layout to achieve an enhanced process latitude regardless of the area impact and applying standard design rules on remaining areas of the target layout, wherein the relaxed rules include priority values for resolving conflicts between relaxed rules whereby a simulated printed image of the new target layout meets the specification.
Claim 35
Dependent Claim
185 words
A mask to be used in an optical lithography process, wherein the mask is created through a method that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, the method comprising: receiving a representation of a target layout for the integrated circuit; wherein the representation defines a plurality of shapes that comprise the target layout; simulating effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout; identifying problem areas in the simulated printed image that do not meet a specification; and moving corresponding shapes in the target layout to produce new target layout for the integrated circuit, wherein moving the corresponding shapes in the target layout involves applying relaxed rules to the problem areas of the target layout to achieve an enhanced process latitude regardless of the area impact and applying standard design rules on remaining areas of the target layout, wherein the relaxed rules include priority values for resolving conflicts between relaxed rules whereby a simulated printed image of the new target layout meets the specification.
Claim 36
Dependent Claim
174 words
An integrated circuit created through a method that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, the method comprising: receiving a representation of a target layout for the integrated circuit; wherein the representation defines a plurality of shapes that comprise the target layout; simulating effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout; identifying problem areas in the simulated printed image that do not meet a specification; and moving corresponding shapes in the target layout to produce new target layout for the integrated circuit, wherein moving the corresponding shapes in the target layout involves applying relaxed rules to the problem areas of the target layout to achieve an enhanced process latitude regardless of the area impact and applying standard design rules on remaining areas of the target layout, wherein the relaxed rules include priority values for resolving conflicts between relaxed rules whereby a simulated printed image of the new target layout meets the specification.
Claim 37
Dependent Claim
174 words
An integrated circuit created through a method that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, the method comprising: receiving a representation of a target layout for the integrated circuit; wherein the representation defines a plurality of shapes that comprise the target layout; simulating effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout; identifying problem areas in the simulated printed image that do not meet a specification; and moving corresponding shapes in the target layout to produce new target layout for the integrated circuit, wherein moving the corresponding shapes in the target layout involves applying relaxed rules to the problem areas of the target layout to achieve an enhanced process latitude regardless of the area impact and applying standard design rules on remaining areas of the target layout, wherein the relaxed rules include priority values for resolving conflicts between relaxed rules whereby a simulated printed image of the new target layout meets the specification.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2007-06-01 | 2007-12-01 | 2008-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-06-01 | 2011-12-01 | 2012-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-06-01 | 2015-12-01 | 2016-06-01 | $7700.00 | Window Closed / Lapsed |