US6415421B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated verification and manufacturability tool
Assignee: Siemens Industry Software Inc
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Filing: 2000-12-22
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Granted: 2002-07-02
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Expires: 2020-12-22
Abstract
Abstract An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.
Inventors
- 👤 Leigh C. Anderson
- 👤 Nicolas B. Cobb
- 👤 Laurence W. Grodd
- 👤 Emile Sahouria
- 👤 Siqiong You
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 10:00
CPC Classifications
G; G03; G03F; G03F1/00; G03F1/26; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398
Claims Analysis
Total Claims: 45
Claim 1
Independent Claim
57 words
An integrated verification and manufacturability tool comprising: a hierarchical database to represent at least a portion of an integrated device layout in a hierarchical manner; a checking component to operate on the integrated device design by accessing said database; and an optical process correction (OPC) component to operate on the integrated device layout by accessing said database.
Claim 2
Dependent Claim
57 words
An integrated verification and manufacturability tool comprising: a hierarchical database to represent at least a portion of an integrated device layout in a hierarchical manner; a checking component to operate on the integrated device design by accessing said database; and an optical process correction (OPC) component to operate on the integrated device layout by accessing said database.
Claim 3
Dependent Claim
21 words
The integrated verification and manufacturability tool of claim 1 , wherein the checking component comprises a layout versus schematic (LVS) component.
Claim 4
Dependent Claim
21 words
The integrated verification and manufacturability tool of claim 1 , wherein the checking component comprises a design rule checking (DRC) component.
Claim 5
Dependent Claim
18 words
The integrated verification and manufacturability tool of claim 1 , further comprising a phase shift mask (PSM) component.
Claim 6
Dependent Claim
18 words
The integrated verification and manufacturability tool of claim 1 , further comprising an optical rule checking (ORC) component.
Claim 7
Dependent Claim
32 words
The integrated verification and manufacturability tool of claim 1 , wherein the OPC component and the checking component operate on sets of edges that represent a portion of the integrated device layout.
Claim 8
Dependent Claim
21 words
The integrated verification and manufacturability tool of claim 1 , wherein the integrated device layout is an integrated circuit (IC) layout.
Claim 9
Dependent Claim
20 words
The integrated verification and manufacturability tool of claim 1 , wherein the hierarchical database includes one or more intermediate layers.
Claim 10
Dependent Claim
40 words
The integrated verification and manufacturability tool of claim 8 , wherein a number of intermediate layers to be included in the hierarchical database is determined based, at least in part, on operations to be performed on the integrated device layout.
Claim 11
Independent Claim
71 words
A method comprising: importing an integrated device layout into a common hierarchical database to create shared data; executing a sequence of program instructions that initiate the operation of one or more checking components that perform layout verification operations on the shared data; and executing a sequence of program instructions that initiate the operation of a distinct optical process correction component that performs optical process correction (OPC) operations on the shared data.
Claim 12
Independent Claim
71 words
A method comprising: importing an integrated device layout into a common hierarchical database to create shared data; executing a sequence of program instructions that initiate the operation of one or more checking components that perform layout verification operations on the shared data; and executing a sequence of program instructions that initiate the operation of a distinct optical process correction component that performs optical process correction (OPC) operations on the shared data.
Claim 13
Dependent Claim
27 words
The method of claim 10 , wherein the one or more checking components include a component that performs layout versus schematic (LVS) operations on the shared data.
Claim 14
Dependent Claim
27 words
The method of claim 10 , wherein the one or more checking components include a component that performs design rule checking (DRC) operations on the shared data.
Claim 15
Dependent Claim
31 words
The method of claim 10 , wherein the one or more checking components include a component that performs design rule checking (DRC) operations on simulated silicon edges within the shared data.
Claim 16
Dependent Claim
32 words
The method of claim 10 , further comprising executing a sequence of program instructions that initiate the operation of a component that performs phase shift mask (PSM) operations on the shared data.
Claim 17
Dependent Claim
33 words
The method of claim 10 , further comprising executing a sequence of program instructions that initiate the operation of a distinct component that performs optical rule checking (ORC) operations on the shared data.
Claim 18
Dependent Claim
42 words
The method of claim 10 , wherein importing an integrated device layout into the hierarchical database comprises analyzing an original integrated device layout for redundant patterns and replacing one or more of the redundant patterns with cells that include the redundant patterns.
Claim 19
Dependent Claim
41 words
The method of claim 10 , wherein importing an integrated device layout into the hierarchical database comprises converting one or more portions of the layout comprising a single layer to one or more portions of the layout comprising multi-level hierarchical layouts.
Claim 20
Dependent Claim
37 words
The method of claim 10 , wherein the layout verification operations and the optical process correction (OPC) operations are performed on a set of edges that represent portions of the integrated device layout within the shared data.
Claim 21
Dependent Claim
17 words
The method of claim 10 , wherein the integrated device layout comprises an integrated circuit (IC) layout.
Claim 22
Dependent Claim
78 words
A machine-readable medium having stored thereon sequences of instructions that, when executed, cause one or more electronic systems to: import an integrated device layout to a common hierarchical database to create shared data; initiate the operation of one or more checking components that perform layout verification operations on the integrated device design on the shared data; and initiate the operation of a distinct optical process correction component that performs optical process correction (OPC) operations on the shared data.
Claim 23
Dependent Claim
78 words
A machine-readable medium having stored thereon sequences of instructions that, when executed, cause one or more electronic systems to: import an integrated device layout to a common hierarchical database to create shared data; initiate the operation of one or more checking components that perform layout verification operations on the integrated device design on the shared data; and initiate the operation of a distinct optical process correction component that performs optical process correction (OPC) operations on the shared data.
Claim 24
Dependent Claim
24 words
The machine-readable medium of claim 20 , wherein the one or more checking components perform layout versus schematic (LVS) operations on the shared data.
Claim 25
Dependent Claim
24 words
The machine-readable medium of claim 20 , wherein the one or more checking components perform design rule checking (DRC) operations on the shared data.
Claim 26
Dependent Claim
40 words
The machine-readable medium of claim 20 , further comprising sequences of instructions that, when executed, cause the one or more electronic systems to initiate the operation of a component that performs phase shift mask (PSM) operations on the shared data.
Claim 27
Dependent Claim
40 words
The machine-readable medium of claim 20 , further comprising sequences of instructions that, when executed, cause the one or more electronic systems to initiate the operation of a component that performs optical rule checking (ORC) operations on the shared data.
Claim 28
Dependent Claim
44 words
The machine-readable medium of claim 20 , further comprising sequences of instructions that, when executed, cause the one or more electronic systems to initiate the operation of a component that performs optical rule checking (ORC) operations on simulated silicon edges within the shared data.
Claim 29
Dependent Claim
69 words
The machine-readable medium of claim 20 , wherein the sequences of instructions that cause the one or more electronic systems to import an integrated device layout into the hierarchical database comprises sequences of instructions that, when executed, cause the one or more electronic systems to analyze an original integrated device layout for redundant patterns and replacing one or more of the redundant patterns with cells that include redundant patterns.
Claim 30
Dependent Claim
69 words
The machine-readable medium of claim 20 , wherein the sequences of instructions that cause the one or more electronic systems to import an integrated device layout to the hierarchical database comprises sequences of instructions that, when executed, cause the one or more electronic systems to convert one or more portions of the layout comprising a single layer to one or more portions of the layout comprising multi-level hierarchical layouts.
Claim 31
Dependent Claim
38 words
The machine-readable medium of claim 20 , wherein the layout verification operations and the optical process correction (OPC) operations are performed on a set of edges the represent portions of the integrated device layout within the shared data.
Claim 32
Dependent Claim
18 words
The machine-readable medium of claim 20 , wherein the integrated device layout comprises an integrated circuit (IC) layout.
Claim 33
Dependent Claim
80 words
An electronic data signal embodied in a data communications medium shared among a plurality of network devices comprising sequences of instructions that, when executed, cause one or more electronic systems to: import an integrated device layout into a hierarchical database; initiate the operation of one or more checking components that perform layout verification operations on the integrated device design; and initiate the operation of a distinct software component that performs optical process correction (OPC) operations on the integrated device design.
Claim 34
Dependent Claim
80 words
An electronic data signal embodied in a data communications medium shared among a plurality of network devices comprising sequences of instructions that, when executed, cause one or more electronic systems to: import an integrated device layout into a hierarchical database; initiate the operation of one or more checking components that perform layout verification operations on the integrated device design; and initiate the operation of a distinct software component that performs optical process correction (OPC) operations on the integrated device design.
Claim 35
Dependent Claim
30 words
The electronic data signal of claim 30 , wherein the one or more checking components include a component that performs layout versus schematic (LVS) operations on the integrated device layout.
Claim 36
Dependent Claim
30 words
The electronic data signal of claim 30 , wherein the one or more checking components include a component that performs design rule checking (DRC) operations on the integrated device layout.
Claim 37
Dependent Claim
42 words
The electronic data signal of claim 30 , further comprising sequences of instructions that, when executed, cause the one or more electronic systems to initiate the operation of a component that performs phase shift mask (PSM) operations on the integrated device layout.
Claim 38
Dependent Claim
42 words
The electronic data signal of claim 30 , further comprising sequences of instructions that, when executed, cause the one or more electronic systems to initiate the operation of a component that performs optical rule checking (ORC) operations on the integrated device layout.
Claim 39
Dependent Claim
41 words
The electronic data signal of claim 30 , further comprising sequences of instructions that, when executed, cause the one or more electronic systems to initiate the operation of a component that performs optical rule checking (ORC) operations on simulated silicon edges.
Claim 40
Dependent Claim
71 words
The electronic data signal of claim 30 , wherein the sequences of instructions that cause the one or more electronic systems to import an integrated device layout to the hierarchical database comprises sequences of instructions that, when executed, cause the one or more electronic systems to analyze an original integrated device design for redundant patterns and replace one or more of the redundant patterns with cells that include the redundant patterns.
Claim 41
Dependent Claim
70 words
The electronic data signal of claim 30 , wherein the sequences of instructions that cause the one or more electronic systems to import an integrated device layout to the hierarchical database comprises sequences of instructions that, when executed, cause the one or more electronic systems to convert one or more portions of the layout comprising a single layer to one or more portions of the layout comprising multi-level hierarchical layouts.
Claim 42
Dependent Claim
35 words
The electronic data signal of claim 30 , wherein the layout verification operations and the optical process correction (OPC) operations are performed on a set of edges the represent portions of the integrated device layout.
Claim 43
Dependent Claim
19 words
The electronic data signal of claim 30 , wherein the integrated device design comprises an integrated circuit (IC) layout.
Claim 44
Dependent Claim
133 words
A machine readable medium on which is stored a sequence of programmed instructions to be executed by one or more processors in order to: create a shared hierarchical database that represents components of an integrated circuit layout having a number of hierarchy layers, wherein redundant patterns of edges and/or polygons are described in the hierarchical database along with indication of where each such redundant pattern is found in the integrated circuit layout; selectively promote edges or polygons in the database that interact to another layer of hierarchy such that each placement of the interacting edges or polygons can be separately analyzed; and initiating a number of checking components and a distinct optical process correction component that analyze the data in the shared hierarchical database to ensure the manufacturability of the integrated circuit layout.
Claim 45
Dependent Claim
133 words
A machine readable medium on which is stored a sequence of programmed instructions to be executed by one or more processors in order to: create a shared hierarchical database that represents components of an integrated circuit layout having a number of hierarchy layers, wherein redundant patterns of edges and/or polygons are described in the hierarchical database along with indication of where each such redundant pattern is found in the integrated circuit layout; selectively promote edges or polygons in the database that interact to another layer of hierarchy such that each placement of the interacting edges or polygons can be separately analyzed; and initiating a number of checking components and a distinct optical process correction component that analyze the data in the shared hierarchical database to ensure the manufacturability of the integrated circuit layout.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-07-01 | 2005-12-31 | 2006-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-07-01 | 2009-12-31 | 2010-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-07-01 | 2013-12-31 | 2014-07-02 | $7700.00 | Window Closed / Lapsed |