US7230876B2
Expired / Lapsed
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Register read for volatile memory
Assignee: Qualcomm Inc
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Filing: 2005-05-13
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Granted: 2007-06-12
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Expires: 2025-05-13
Abstract
Abstract Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read command/operation directed to data stored in the DRAM array in timing and operation. The register read command is distinguished by a unique encoding of the SDRAM control signals and bank address bits. In one embodiment, the register read command comprises the same control signal states as a MSR or EMSR command, with the bank address set to a unique value, such as 2'b10. The register read command may read only a single datum, or may utilize the address bus to address a plurality of data not stored in the DRAM array. The register read operation may be a burst read, and the burst length may be defined in a variety of ways.
Inventors
- 👤 Robert Michael Walker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 10:25
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/40626; G11C7/00; G11C7/10; G11C7/1015; G11C7/1045; G11C7/1072; G11C2211/00; G11C2211/401; G11C2211/406; G11C2211/4061
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
56 words
A method of reading data from a SDRAM (Synchronous Dynamic Access Ram) module, that is not stored in a DRAM Dynamic Access Ram) array, comprising: providing control signals for a synchronous read of data from a DRAM array with a unique encoding of control signals; and synchronously reading the data not stored in a DRAM array.
Claim 2
Independent Claim
56 words
A method of reading data from a SDRAM (Synchronous Dynamic Access Ram) module, that is not stored in a DRAM Dynamic Access Ram) array, comprising: providing control signals for a synchronous read of data from a DRAM array with a unique encoding of control signals; and synchronously reading the data not stored in a DRAM array.
Claim 3
Dependent Claim
33 words
The method of claim 1 wherein synchronously reading the data not stored in a DRAM array comprises synchronously reading the data not stored in a DRAM array when a DRAM row is open.
Claim 4
Dependent Claim
20 words
The method of claim 1 wherein the data not stored in a DRAM array comprises the contents of a register.
Claim 5
Dependent Claim
20 words
The method of claim 3 wherein the register is a MSR (Mode Register Set) or EMSR (Extended Mode Register Set).
Claim 6
Dependent Claim
20 words
The method of claim 1 wherein the data not stored in a DRAM array comprises the output of a sensor.
Claim 7
Dependent Claim
32 words
The method of claim 5 wherein the sensor is a temperature sensor and wherein the data not stored in a DRAM array is indicative of the internal temperature of the memory module.
Claim 8
Dependent Claim
20 words
The method of claim 6 , wherein the data not stored in a DRAM array is a refresh rate multiplier.
Claim 9
Dependent Claim
21 words
The method of claim 6 , further comprising adjusting a refresh rate in response to the temperature of the memory module.
Claim 10
Dependent Claim
20 words
The method of claim 1 wherein the data not stored in a DRAM array is hardwired in the memory module.
Claim 11
Dependent Claim
35 words
The method of claim 1 wherein the unique encoding of control signals is the encoding for a write of a register, with a bank address distinct from any bank address defined for a register write.
Claim 12
Dependent Claim
22 words
The method of claim 10 wherein the RAS, CAS, and WE control signals are low, and wherein the bank address is 2'b10.
Claim 13
Dependent Claim
31 words
The method of claim 1 , further comprising reading or writing data from or to a DRAM array immediately before or after reading the data not stored in a DRAM array.
Claim 14
Dependent Claim
29 words
The method of claim 1 where synchronously reading the data not stored in a DRAM array comprises reading the data not stored in a DRAM array in a burst.
Claim 15
Dependent Claim
25 words
The method of claim 13 wherein the burst length is determined by the burst length for synchronous reads of data stored in the DRAM array.
Claim 16
Dependent Claim
67 words
The method of claim 13 further comprising programming a burst length for read bursts of data not stored in a DRAM array in a register on the memory module, that is different than the burst length for synchronous reads of data stored in the DRAM array, and wherein the burst length is the programmed burst length for read bursts of data not stored in a DRAM array.
Claim 17
Dependent Claim
39 words
The method of claim 13 wherein the burst length is a predetermined default value, independent of a burst length for read bursts of data stored in a DRAM array that is programmed into a register on the memory module.
Claim 18
Dependent Claim
19 words
The method of claim 13 wherein the burst length is encoded in control signals output to the memory module.
Claim 19
Dependent Claim
15 words
The method of claim 13 wherein the burst length is encoded in unused address bits.
Claim 20
Dependent Claim
56 words
An SDRAM memory module, comprising: a DRAM array; a register; and control circuits operative to perform synchronous data transfers with a controller and to read and write data from and to the DRAM array, the control circuits further operative to output to the controller, in a synchronous data transfer, data not stored in the DRAM array.
Claim 21
Dependent Claim
56 words
An SDRAM memory module, comprising: a DRAM array; a register; and control circuits operative to perform synchronous data transfers with a controller and to read and write data from and to the DRAM array, the control circuits further operative to output to the controller, in a synchronous data transfer, data not stored in the DRAM array.
Claim 22
Dependent Claim
38 words
The memory module of claim 19 wherein the control circuits are operative to output data not stored in the DRAM array to the controller in a synchronous data transfer when a row of the DRAM array is open.
Claim 23
Dependent Claim
21 words
The memory module of claim 19 wherein the synchronous data transfer includes a unique encoding of control signals from the controller.
Claim 24
Dependent Claim
36 words
The memory module of claim 21 wherein the unique encoding of control signals is the encoding for a write of a register, with a bank address distinct from any bank address defined for a register write.
Claim 25
Dependent Claim
23 words
The memory module of claim 22 wherein the RAS, CAS, and WE control signals are low, and wherein the bank address is 2'b10.
Claim 26
Dependent Claim
15 words
The memory module of claim 19 wherein the synchronous data transfer is a burst transfer.
Claim 27
Dependent Claim
47 words
The memory module of claim 24 wherein the register stores a burst length for read transfers of data from the DRAM array, and wherein the burst length for the synchronous data transfer of data not stored in a DRAM array is determined by the stored burst length.
Claim 28
Dependent Claim
58 words
The memory module of claim 24 wherein the register stores a burst length for read transfers of data not from the DRAM array, and wherein the burst length for the synchronous data transfer of data not stored in a DRAM array is determined by the stored burst length for read transfers of data not from the DRAM array.
Claim 29
Dependent Claim
24 words
The memory module of claim 24 wherein the burst length is a predetermined default value, independent of any burst length stored in a register.
Claim 30
Dependent Claim
19 words
The memory module of claim 24 wherein the burst length is encoded in the control signals from the controller.
Claim 31
Dependent Claim
16 words
The memory module of claim 24 wherein the burst length is encoded in unused address bits.
Claim 32
Dependent Claim
21 words
The memory module of claim 19 wherein the data not stored in the DRAM array comprises the contents of the register.
Claim 33
Dependent Claim
21 words
The memory module of claim 19 wherein the data not stored in the DRAM array is hardwired in the memory module.
Claim 34
Dependent Claim
26 words
The memory module of claim 19 further comprising a sensor, and wherein the data not stored in the DRAM array comprises the output of the sensor.
Claim 35
Dependent Claim
31 words
The memory module of claim 32 wherein the sensor is a temperature sensor, and wherein the data not stored in the DRAM array represents the internal temperature of the memory module.
Claim 36
Dependent Claim
20 words
The memory module of claim 33 wherein the data not stored in the DRAM array is a refresh rate multiplier.
Claim 37
Dependent Claim
39 words
The memory module of claim 19 wherein the control circuits are operative to perform synchronous transfers of data from or to the DRAM array immediately before or after outputting to the controller data not stored in the DRAM array.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-06-11 | 2010-12-11 | 2011-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-06-11 | 2014-12-11 | 2015-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-06-11 | 2018-12-11 | 2019-06-12 | $7700.00 | Window Closed / Lapsed |