Mode register control circuit and semiconductor device having the same

Claim 2

The mode register control circuit (10) as claimed in claim 1, wherein a content of the mode register is prevented from being read out by using an initializing signal for initializing a latch part for latching an external command and/or an external address externally fed to the semiconductor device (40) when said latch part is supplied with power.

Claim 3

A mode register control circuit (10) provided in a semiconductor device (40) and controlling operation of reading from a mode register of the semiconductor device (40) in response to an external command signal, said mode register control circuit (10) comprising a second control unit (104) which instructs, upon determining that a command other than a mode register read command instructing a content of the mode register to be read out is detected when the semiconductor device (40) is supplied with power, the mode register to execute the mode register read command even if a mode register set command has not been executed after a power supply voltage becomes stable.

Claim 4

A mode register control circuit (10) provided in a semiconductor device (40) and controlling operation of reading from a mode register of the semiconductor device (40) in response to an external command signal, said mode register control circuit (10) comprising a third control unit (106) which instructs, upon detecting that a mode register set command has been executed after the semiconductor is supplied with power, the mode register to execute a mode register read command instructing a content of the mode register to be read out.

Claim 5

The mode register control circuit (10) as claimed in claim 3, comprising a third control unit (106) which instructs, upon detecting that the mode register set command has been executed after the semiconductor is supplied with power, the mode register to execute the mode register read command.

Claim 6

The mode register control circuit (10) as claimed in claim 4, comprising a second control unit (104) which instructs, upon determining that a command other than the mode register read command is detected when the semiconductor device (40) is supplied with power, the mode register to execute the mode register read command even if the mode register set command has not been executed after a power supply voltage becomes stable.

Claim 7

A semiconductor device (40) comprising: a starter signal generating circuit (101) for generating an initializing signal for initializing a latching circuit when the semiconductor device (40) is turned on; an internal clock generating unit (102) for generating an internal clock signal in correspondence with an external clock signal; a memory cell array (113); a read/write circuit (130) for reading data from and writing data to the memory cell array (113); an input/output circuit (140) for inputting and outputting data addresses and commands; a mode register (20) for latching an operation mode of the input/output circuit (140); a mode register control circuit (111) for controlling operation of reading from the mode register (20), wherein said mode register control circuit (111) is provided in a semiconductor device (40), controls operation of reading from the mode register (20) of the semiconductor device (40) in response to an external command signal, and comprises a first control unit (102) for preventing a content of the mode register from being read out from the semiconductor device (40), when the semiconductor device (40) beings to be supplied with power.

Claim 8

The semiconductor device (40) as claimed in claim 7, wherein a content of the mode register (20) is prevented from being read out by using an initializing signal for initializing a latch part for latching an external command and/or an external address externally fed to the semiconductor device (40) when said latch part is supplied with power.

Claim 9

A semiconductor device (40) comprising: a starter signal generating circuit (101) for generating an initializing signal for initializing a latching circuit when the semiconductor device (40) is turned on; an internal clock generating unit (102) for generating an internal clock signal in correspondence with an external clock signal; a memory cell array (113); a read/write circuit (130) for reading data from and writing data to the memory cell array (113); an input/output circuit (140) for inputting and outputting data addresses and commands; a mode register (20) for latching an operation mode of the input/output circuit (140); a mode register control circuit (111) for controlling operation of reading from the mode register (20), wherein said mode register control circuit (111) is provided in a semiconductor device (40), controls operation of reading from the mode register (20) of the semiconductor device (40) in response to an external command signal and comprises a second control unit (104) which instructs, upon determining that a command other than a mode register read command instructing a content of the mode register (20) to be read out is detected when the semiconductor device (40) is supplied with power, the mode register (20) to execute the mode register read command even if a mode register set command has not been executed after a power supply voltage becomes stable.

Claim 10

A semiconductor device (40) comprising: a starter signal generating circuit (101) for generating an initializing signal for initializing a latching circuit when the semiconductor device (40) is turned on; an internal clock generating unit (102) for generating an internal clock signal in correspondence with an external clock signal; a memory cell array (113); a read/write circuit (130) for reading data from and writing data to the memory cell array (113); an input/output circuit (140) for inputting and outputting data addresses and commands; a mode register (20) for latching an operation mode of the input/output circuit (140); a mode register control circuit (111) for controlling operation of reading from the mode register (20), wherein said mode register control circuit (111) is provided in a semiconductor device (40), controls operation of reading from the mode register (20) of the semiconductor device (40) in response to an external command signal, and comprises a third control unit (106) which instructs, upon detecting that a mode register set command has been executed after the semiconductor is supplied with power, the mode register (20) to execute a mode register read command instructing a content of the mode register (20) to be read out.

Claim 11

The semiconductor device (40) as claimed in claim 9, wherein the mode register control unit (111) comprises a third control unit (106) which instructs, upon detecting that the mode register set command has been executed after the semiconductor is supplied with power, the mode register (20) to execute the mode register read command.

Claim 12

The semiconductor device (40) as claimed in claim 10, wherein the mode register control circuit (111) comprises a second control unit (104) which instructs, upon determining that a command other than the mode register read command is detected when the semiconductor device (40) is supplied with power, the mode register (20) to execute the mode register read command even if the mode register set command has not been executed after a power supply voltage becomes stable.