Display system

Claim 2

A display system comprising: a plurality of pixels, each of the plurality of pixels comprising a first thin film transistors over a substrate having an insulating surface; a driver circuit for outputting an inputted image signal to the plurality of pixels, the driver circuit comprising a second thin film transistor over the substrate; and a first means for storing the image signal to be outputted to the driver circuit, the first means comprising a third thin film transistor over the substrate, wherein each of the first to the third thin film transistors comprises a first electrode and a second electrode overlapped with a first channel region though insulating films, wherein the first electrode and the second electrode are overlapped with each other so as to sandwich the first channel region therebetween, wherein each of the plurality of pixels comprises a fourth thin film transistor connected to a light emitting element, wherein the fourth thin film transistor comprises a third electrode and a fourth electrode overlapped with each other so as to sandwich a second channel region therebetween and connected to each other, wherein the first thin film transistor further comprises a fifth electrode connected to the second electrode and overlapped with the first electrode through the insulating film, wherein the first electrode and the fifth electrode are overlapped with each other so as to sandwich a third channel region therebetween, and wherein an LDD region is interposed between the third channel region and the first channel region.

Claim 3

A display system according to claim 1 , wherein a potential of the first electrode of the plurality of first thin film transistors is kept to be constant.

Claim 4

A display system according to claim 1 , wherein the first electrode and the second electrode of the plurality of second and third thin film transistors are electrically connected with each other so as to be applied same voltage to both electrodes.

Claim 5

A display system according to claim 1 , wherein a potential difference between a potential of a source region and the first electrode is set to be a threshold of the first thin film transistors or lower than the threshold when the plurality of first thin film transistors are n-channel type.

Claim 6

A display system according to claim 1 , wherein a potential difference between a potential of a source region and the first electrode is set to be a threshold of the first thin film transistors or higher than the threshold when the plurality of first thin film transistors are p-channel type.

Claim 7

A display system according to claim 1 , wherein the display system is incorporated at least in one selected from the group consisting of a personal digital assistant, a personal computer, an image reproduction device, a television, a head mounted display, and a camera.

Claim 8

A display system comprising: a plurality of pixels, each of the plurality of pixels comprising a first thin film transistors over a substrate having an insulating surface; a driver circuit for outputting an inputted image signal to the plurality of pixels, the driver circuit comprising second thin film transistor over the substrate; and a first means for storing the image signal to be outputted to the driver circuit, the first means comprising a third thin film transistor over the substrate, a second means for determining a drive frequency of the driver circuit, the second means comprising a fourth thin film transistor over the substrate, wherein each of the first to the fourth thin film transistors comprises a first electrode and a second electrode overlapped with a first channel region through insulating films, wherein the first electrode and the second electrode are overlapped with each other so as to sandwich the first channel region therebetween, wherein each of the plurality of pixels comprises a fifth thin film transistor connected to a light emitting element, wherein the fifth thin film transistor comprises a third electrode and a fourth electrode overlapped with each other so as to sandwich a second channel region therebetween and connected to each other, wherein the first thin film transistor further comprises a fifth electrode connected to the second electrode and overlapped with the first electrode through the insulating film, wherein the first electrode and the fifth electrode are overlapped with each other so as to sandwich a third channel region therebetween, and wherein an LDD region is interposed between the third channel region and the first channel region.

Claim 9

A display system comprising: a plurality of pixels, each of the plurality of pixels comprising a first thin film transistors over a substrate having an insulating surface; a driver circuit for outputting an inputted image signal to the plurality of pixels, the driver circuit comprising second thin film transistor over the substrate; and a first means for storing the image signal to be outputted to the driver circuit, the first means comprising a third thin film transistor over the substrate, a second means for determining a drive frequency of the driver circuit, the second means comprising a fourth thin film transistor over the substrate, wherein each of the first to the fourth thin film transistors comprises a first electrode and a second electrode overlapped with a first channel region through insulating films, wherein the first electrode and the second electrode are overlapped with each other so as to sandwich the first channel region therebetween, wherein each of the plurality of pixels comprises a fifth thin film transistor connected to a light emitting element, wherein the fifth thin film transistor comprises a third electrode and a fourth electrode overlapped with each other so as to sandwich a second channel region therebetween and connected to each other, wherein the first thin film transistor further comprises a fifth electrode connected to the second electrode and overlapped with the first electrode through the insulating film, wherein the first electrode and the fifth electrode are overlapped with each other so as to sandwich a third channel region therebetween, and wherein an LDD region is interposed between the third channel region and the first channel region.

Claim 10

A display system according to claim 7 , wherein a potential of the first electrode of the plurality of first thin film transistors is kept to be constant.

Claim 11

A display system according to claim 7 , wherein the first electrode and the second electrode of the plurality of second to fourth thin film transistors are electrically connected with each other so as to be applied same voltage to both electrodes.

Claim 12

A display system according to claim 7 , wherein a potential difference between a potential of a source region and the first electrode is set to be a threshold of the first thin film transistors or lower than the threshold when the plurality of first thin film transistors are n-channel type.

Claim 13

A display system according to claim 7 , wherein a potential difference between a potential of a source region and the first electrode is set to be a threshold of the first thin film transistors or higher than the threshold when the plurality of first thin film transistors are p-channel type.

Claim 14

A display system according to claim 7 , wherein the display system is incorporated at least in one selected from the group consisting of a personal digital assistant, a personal computer, an image reproduction device, a television, a head mounted display, and a camera.

Claim 15

A display system comprising: a plurality of pixels, each of the plurality of pixels comprising a first thin film transistors over a substrate having an insulating surface; a driver circuit for outputting an inputted image signal to the plurality of pixels, the driver circuit comprising a second thin film transistor over the substrate; and a memory for storing the image signal to be outputted to the driver circuit, the memory comprising a third thin film transistor over the substrate, wherein each of the first to the third thin film transistors comprises a first electrode and a second electrode overlapped with a first channel region through insulating films, wherein the first electrode and the second electrode are overlapped with each other so as to sandwich the first channel region therebetween, wherein each of the plurality of pixels comprises a fourth thin film transistor connected to a light emitting element, wherein the fourth thin film transistor comprises a third electrode and a fourth electrode overlapped with each other so as to sandwich a second channel region therebetween and connected to each other, wherein the first thin film transistor further comprises a fifth electrode connected to the second electrode and overlapped with the first electrode through the insulating film, wherein the first electrode and the fifth electrode are overlapped with each other so as to sandwich a third channel region therebetween, and wherein an LDD region is interposed between the third channel region and the first channel region.

Claim 16

A display system comprising: a plurality of pixels, each of the plurality of pixels comprising a first thin film transistors over a substrate having an insulating surface; a driver circuit for outputting an inputted image signal to the plurality of pixels, the driver circuit comprising a second thin film transistor over the substrate; and a memory for storing the image signal to be outputted to the driver circuit, the memory comprising a third thin film transistor over the substrate, wherein each of the first to the third thin film transistors comprises a first electrode and a second electrode overlapped with a first channel region through insulating films, wherein the first electrode and the second electrode are overlapped with each other so as to sandwich the first channel region therebetween, wherein each of the plurality of pixels comprises a fourth thin film transistor connected to a light emitting element, wherein the fourth thin film transistor comprises a third electrode and a fourth electrode overlapped with each other so as to sandwich a second channel region therebetween and connected to each other, wherein the first thin film transistor further comprises a fifth electrode connected to the second electrode and overlapped with the first electrode through the insulating film, wherein the first electrode and the fifth electrode are overlapped with each other so as to sandwich a third channel region therebetween, and wherein an LDD region is interposed between the third channel region and the first channel region.

Claim 17

A display system according to claim 13 , wherein a potential of the first electrode of the plurality of first thin film transistors is kept to be constant.

Claim 18

A display system according to claim 13 , wherein the first electrode and the second electrode of the plurality of second to third thin film transistors are electrically connected with each other so as to be applied same voltage to both electrodes.

Claim 19

A display system according to claim 13 , wherein a potential difference between a potential of a source region and the first electrode is set to be a threshold of the first thin film transistors or lower than the threshold when the plurality of first thin film transistors are n-channel type.

Claim 20

A display system according to claim 13 , wherein a potential difference between a potential of a source region and the first electrode is set to be a threshold of the first thin film transistors or higher than the threshold when the plurality of first thin film transistors are p-channel type.

Claim 21

A display system according to claim 13 , wherein the memory comprises a SRAM circuit.

Claim 22

A display system according to claim 13 , wherein the display system is incorporated at least in one selected from the group consisting of a personal digital assistant, a personal computer, an image reproduction device, a television, a head mounted display, and a camera.

Claim 23

A display system comprising: a plurality of pixels, each of the plurality of pixels comprising a first thin film transistors over a substrate having an insulating surface; a driver circuit for outputting an inputted image signal to the plurality of pixels, the driver circuit comprising a second thin film transistor over the substrate; and a memory for storing the image signal to be outputted to the driver circuit, the memory comprising a plurality of third thin film transistor over the substrate, a memory controller for assigning an address of the memory and outputting a write signal and a read signal, the memory controller comprising a fourth thin film transistor over the substrate, wherein each of the first to the fourth thin film transistors comprises a first electrode and a second electrode overlapped with a first channel region through insulating films, wherein the first electrode and the second electrode are overlapped with each other so as to sandwich the first channel region therebetween, wherein each of the plurality of pixels comprises a fifth thin film transistor connected to a light emitting element, wherein the fifth thin film transistor comprises a third electrode and a fourth electrode overlapped with each other so as to sandwich a second channel region therebetween and connected to each other, wherein the first thin film transistor further comprises a fifth electrode connected to the second electrode and overlapped with the first electrode through the insulating film, wherein the first electrode and the fifth electrode are overlapped with each other so as to sandwich a third channel region therebetween, and wherein an LDD region is interposed between the third channel region and the first channel region.

Claim 24

A display system comprising: a plurality of pixels, each of the plurality of pixels comprising a first thin film transistors over a substrate having an insulating surface; a driver circuit for outputting an inputted image signal to the plurality of pixels, the driver circuit comprising a second thin film transistor over the substrate; and a memory for storing the image signal to be outputted to the driver circuit, the memory comprising a plurality of third thin film transistor over the substrate, a memory controller for assigning an address of the memory and outputting a write signal and a read signal, the memory controller comprising a fourth thin film transistor over the substrate, wherein each of the first to the fourth thin film transistors comprises a first electrode and a second electrode overlapped with a first channel region through insulating films, wherein the first electrode and the second electrode are overlapped with each other so as to sandwich the first channel region therebetween, wherein each of the plurality of pixels comprises a fifth thin film transistor connected to a light emitting element, wherein the fifth thin film transistor comprises a third electrode and a fourth electrode overlapped with each other so as to sandwich a second channel region therebetween and connected to each other, wherein the first thin film transistor further comprises a fifth electrode connected to the second electrode and overlapped with the first electrode through the insulating film, wherein the first electrode and the fifth electrode are overlapped with each other so as to sandwich a third channel region therebetween, and wherein an LDD region is interposed between the third channel region and the first channel region.

Claim 25

A display system according to claim 20 , wherein a potential of the first electrode of the plurality of first thin film transistors is kept to be constant.

Claim 26

A display system according to claim 20 , wherein the first electrode and the second electrode of the plurality of second to fourth thin film transistors are electrically connected with each other so as to be applied same voltage to both electrodes.

Claim 27

A display system according to claim 20 , wherein a potential difference between a potential of a source region and the first electrode is set to be a threshold of the first thin film transistors or lower than the threshold when the plurality of first thin film transistors are n-channel type.

Claim 28

A display system according to claim 20 , wherein a potential difference between a potential of a source region and the first electrode is set to be a threshold or of the first thin film transistors higher than the threshold when the plurality of first thin film transistors are p-channel type.

Claim 29

A display system according to claim 20 , wherein the memory comprises a SRAM circuit.

Claim 30

A display system according to claim 20 , wherein the display system is incorporated at least in one selected from the group consisting of a personal digital assistant, a personal computer, an image reproduction device, a television, a head mounted display, and a camera.

Claim 31

A display system comprising: a plurality of pixels, each of the plurality of pixels comprising a first thin film transistors over a substrate having an insulating surface; a driver circuit for outputting an inputted image signal to the plurality of pixels, the driver circuit comprising a second thin film transistor over the substrate; and a memory for storing the image signal to be outputted to the driver circuit, the memory comprising a third thin film transistor over the substrate, a memory controller for assigning an address of the memory and outputting a write signal and a read signal, the memory controller comprising a fourth thin film transistor over the substrate, a CPU for outputting a signal to the memory controller, the CPU comprising a fifth thin film transistor over the substrate, wherein each of the plurality of first to fifth thin film transistors comprises a first electrode and a second electrode overlapped with a first channel region through insulating films, wherein the first electrode and the second electrode are overlapped with each other so as to sandwich the first channel region therebetween, wherein each of the plurality of pixels comprises a sixth thin film transistor connected to a light emitting element, wherein the sixth thin film transistor comprises a third electrode and a fourth electrode overlapped with each other so as to sandwich a second channel region therebetween and connected to each other, wherein the first thin film transistor further comprises a fifth electrode connected to the second electrode and overlapped with the first electrode through the insulating film, wherein the first electrode and the fifth electrode are overlapped with each other so as to sandwich a third channel region therebetween, and wherein an LDD region is interposed between the third channel region and the first channel region.

Claim 32

A display system comprising: a plurality of pixels, each of the plurality of pixels comprising a first thin film transistors over a substrate having an insulating surface; a driver circuit for outputting an inputted image signal to the plurality of pixels, the driver circuit comprising a second thin film transistor over the substrate; and a memory for storing the image signal to be outputted to the driver circuit, the memory comprising a third thin film transistor over the substrate, a memory controller for assigning an address of the memory and outputting a write signal and a read signal, the memory controller comprising a fourth thin film transistor over the substrate, a CPU for outputting a signal to the memory controller, the CPU comprising a fifth thin film transistor over the substrate, wherein each of the plurality of first to fifth thin film transistors comprises a first electrode and a second electrode overlapped with a first channel region through insulating films, wherein the first electrode and the second electrode are overlapped with each other so as to sandwich the first channel region therebetween, wherein each of the plurality of pixels comprises a sixth thin film transistor connected to a light emitting element, wherein the sixth thin film transistor comprises a third electrode and a fourth electrode overlapped with each other so as to sandwich a second channel region therebetween and connected to each other, wherein the first thin film transistor further comprises a fifth electrode connected to the second electrode and overlapped with the first electrode through the insulating film, wherein the first electrode and the fifth electrode are overlapped with each other so as to sandwich a third channel region therebetween, and wherein an LDD region is interposed between the third channel region and the first channel region.

Claim 33

A display system according to claim 27 , wherein a potential of the first electrode of the plurality of first thin film transistors is kept to be constant.

Claim 34

A display system according to claim 27 , wherein the first electrode and the second electrode of the plurality of second to fifth thin film transistors are electrically connected with each other so as to be applied same voltage to both electrodes.

Claim 35

A display system according to claim 27 , wherein a potential difference between a potential of a source region and the first electrode is set to be a threshold of the first thin film transistors or lower than the threshold when the plurality of first thin film transistors are n-channel type.

Claim 36

A display system according to claim 27 , wherein a potential difference between a potential of a source region and the first electrode is set to be a threshold of the first thin film transistors or higher than the threshold when the plurality of first thin film transistors are p-channel type.

Claim 37

A display system according to claim 27 , wherein the memory comprises a SRAM circuit.

Claim 38

A display system according to claim 27 , wherein the display system is incorporated at least in one selected from the group consisting of a personal digital assistant, a personal computer, an image reproduction device, a television, a head mounted display, and a camera.

Claim 39

A display system comprising: a plurality of pixels, each of the plurality of pixels comprising a first thin film transistors over a substrate having an insulating surface; a driver circuit for outputting an inputted image signal to the plurality of pixels, the driver circuit comprising a second thin film transistor over the substrate; and a memory for storing the image signal to be outputted to the driver circuit, the memory comprising a third thin film transistor over the substrate, a memory controller for assigning an address of the memory and outputting a write signal and a read signal, the memory controller comprising a fourth thin film transistor over the substrate, a CPU for outputting a signal to the memory controller, the CPU comprising a fifth thin film transistor over the substrate, a display controller for outputting a clock pulse and a start pulse to the driver circuit, the display controller comprising a sixth thin film transistor over the substrate, wherein each of the first to the sixth thin film transistors comprises a first electrode and a second electrode overlapped with a first channel region through insulating films, wherein the first electrode and the second electrode are overlapped with each other so as to sandwich the first channel region therebetween, wherein each of the plurality of pixels comprises a seventh thin film transistor connected to a light emitting element, wherein the seventh thin film transistor comprises a third electrode and a fourth electrode overlapped with each other so as to sandwich a channel region therebetween and connected to each other, wherein the first thin film transistor further comprises a fifth electrode connected to the second electrode and overlapped with the first electrode through the insulating film, wherein the first electrode and the fifth electrode are overlapped with each other so as to sandwich a third channel region therebetween, and wherein an LDD region is interposed between the third channel region and the first channel region.

Claim 40

A display system comprising: a plurality of pixels, each of the plurality of pixels comprising a first thin film transistors over a substrate having an insulating surface; a driver circuit for outputting an inputted image signal to the plurality of pixels, the driver circuit comprising a second thin film transistor over the substrate; and a memory for storing the image signal to be outputted to the driver circuit, the memory comprising a third thin film transistor over the substrate, a memory controller for assigning an address of the memory and outputting a write signal and a read signal, the memory controller comprising a fourth thin film transistor over the substrate, a CPU for outputting a signal to the memory controller, the CPU comprising a fifth thin film transistor over the substrate, a display controller for outputting a clock pulse and a start pulse to the driver circuit, the display controller comprising a sixth thin film transistor over the substrate, wherein each of the first to the sixth thin film transistors comprises a first electrode and a second electrode overlapped with a first channel region through insulating films, wherein the first electrode and the second electrode are overlapped with each other so as to sandwich the first channel region therebetween, wherein each of the plurality of pixels comprises a seventh thin film transistor connected to a light emitting element, wherein the seventh thin film transistor comprises a third electrode and a fourth electrode overlapped with each other so as to sandwich a channel region therebetween and connected to each other, wherein the first thin film transistor further comprises a fifth electrode connected to the second electrode and overlapped with the first electrode through the insulating film, wherein the first electrode and the fifth electrode are overlapped with each other so as to sandwich a third channel region therebetween, and wherein an LDD region is interposed between the third channel region and the first channel region.

Claim 41

A display system according to claim 34 , wherein a potential of the first electrode of the plurality of first thin film transistors is kept to be constant.

Claim 42

A display system according to claim 34 , wherein the first electrode and the second electrode of the plurality of second to sixth thin film transistors are electrically connected with each other so as to be applied same voltage to both electrodes.

Claim 43

A display system according to claim 34 , wherein a potential difference between a potential of a source region and the first electrode is set to be a threshold of the first thin film transistors or lower than the threshold when the plurality of first thin film transistors are n-channel type.

Claim 44

A display system according to claim 34 , wherein a potential difference between a potential of a source region and the first electrode is set to be a threshold of the first thin film transistors or higher than the threshold when the plurality of the first thin film transistors are p-channel type.

Claim 45

A display system according to claim 34 , wherein the memory comprises a SRAM circuit.

Claim 46

A display system according to claim 34 , wherein the display system is incorporated at least in one selected from the group consisting of a personal digital assistant, a personal computer, an image reproduction device, a television, a head mounted display, and a camera.