Gradation control for an active matrix EL display

Claim 2

A device according to claim 1, wherein said switching TFT, the EL driving TFT, and the eliminating TFT are at least one of an N channel TFT or a P channel TFT.

Claim 3

A device according to claim 1, wherein said EL driving TFT becomes an OFF state when an electric potential of said power supply line is applied to said gate electrode of said EL driving TFT.

Claim 4

A computer, which uses said electronic device according to claim 1.

Claim 5

A video camera, which uses said electronic device according to claim 1.

Claim 6

A DVD player, which uses said electronic device according to claim 1.

Claim 7

An electronic device comprising: a source signal line driver circuit connected to a plurality of source signal lines; a first gate signal line driver circuit connected to a plurality of first gate signal lines; a second gate signal line driver circuit connected to a plurality of second gate signal lines; a pixel portion including a plurality of pixels; and a power supply line, wherein said plurality of pixels each have a switching TFT, an EL driving TFT, an eliminating TFT, and an EL element, wherein a gate electrode of said switching TFT is connected to said first gate signal line, wherein one of a source region and a drain region of said switching TFT is connected to said plurality of source signal lines, and another thereof is connected to a gate electrode of said EL driving TFT, wherein a gate electrode of said eliminating TFT is connected to said second gate signal line, wherein one of a source region and a drain region of said eliminating TFT is connected to said power supply line, and another thereof is connected to said gate electrode of said EL driving TFT, and wherein one of a source region and a drain region of said EL driving TFT is connected to said power supply line, and another thereof is connected to said EL element.

Claim 8

A device according to claim 7, wherein said switching TFT, the EL driving TFT, and the eliminating TFT are at least one of an N channel TFT or a P channel TFT.

Claim 9

A device according to claim 7, wherein said EL driving TFT becomes an OFF state when an electric potential of said power supply line is applied to said gate electrode of said EL driving TFT.

Claim 10

A computer, which uses said electronic device according to claim 7.

Claim 11

A video camera, which uses said electronic device according to claim 7.

Claim 12

A DVD player, which uses said electronic device according to claim 7.

Claim 13

An electronic device comprising: a source signal line driver circuit connected to a plurality of source signal lines; a first gate signal line driver circuit connected to a plurality of first gate signal lines; a second gate signal line driver circuit connected to a plurality of second gate signal lines; a pixel portion including a plurality of pixels; and a power supply line held at a constant electric potential, wherein said plurality of pixels each have a switching TFT, an EL driving TFT, an eliminating TFT and an EL element; wherein said EL element includes a pixel electrode. an opposing electrode held at a constant electric potential, and an EL layer formed between said pixel electrode and said opposing electrode, wherein a gate electrode of said switching TFT is connected to said first gate signal lines, wherein one of a source region and a drain region of said switching TFT is connected to said plurality of source signal lines, and another thereof is connected to a gate electrode of said EL driving TFT, wherein a gate electrode of said eliminating TFT is connected to said second gate signal lines, wherein one of a source region and a drain region of said eliminating TFT is connected to said power supply line, and another is connected to a gate electrode of said EL driving TFT, and wherein one of a source region and a drain region of said EL driving TFT is connected to said power supply line, and another is connected to a pixel electrode of said EL element.

Claim 14

A device according to claim 13, wherein said EL layer is a low molecular organic material or a polymer organic material.

Claim 15

A device according to claim 14, wherein said low molecular organic material is made of Alq 3 (tris-8-quinolilite-aluminum) or TPD (triphenylamine derivative).

Claim 16

A device according to claim 14, wherein said polymer organic material is made of PPV (polyphenylene vinylene), PVK (polyvinyl carbazole), or polycarbonate.

Claim 17

A device according to claim 13, wherein said switching TFT, the EL driving TFT, and the eliminating TFT are at least one of an N channel TFT or a P channel TFT.

Claim 18

A device according to claim 13, wherein said EL driving TFT becomes an OFF state when an electric potential of said power supply line is applied to said gate electrode of said EL driving TFT.

Claim 19

A computer, which uses said electronic device according claim 13.

Claim 20

A video camera, which uses said electronic device according claim 13.

Claim 21

A DVD player, which uses said electronic device according to claim 13.

Claim 22

An electronic device comprising a source signal line driver circuit, a first gate signal line driver circuit, a second gate signal line driver circuit, a pixel portion including a plurality of pixels, a plurality of source signal lines connected to said source signal line driver circuit, a plurality of first gate signal lines connected to said first gate signal line driver circuit, a plurality of second gate signal lines connected to said second gate signal line driver circuit, and a power supply line, wherein said plurality of pixels each have a switching TFT, an EL driving TFT, an eliminating TFT, and an EL element; a gate electrode of said switching TFT is connected to said first gate signal lines; one of a source region and a drain region of said switching TFT is connected to said plurality of source signal lines, and another thereof is connected to a gate electrode of said EL driving TFT; a gate electrode of said eliminating TFT is connected to said second gate signal lines; one of a source region and a drain region of said eliminating TFT is connected to said power supply line, and another thereof is connected a gate electrode of said EL driving TFT; one of a source region and a drain region of said EL driving TFT is connected to said power supply line, and another thereof is connected to said EL element; an (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) and an (m-1) number of eliminating periods Te1, Te2, ···, Te(m-1) (m is an arbitrary integer from 2 to (n)) are provided in 1 frame period; digital data signals from said source signal line driver circuit are fed to all said plurality of pixels through said plurality of source signal lines in said writing in periods Tal. Ta2, ···, Ta(n); the digital data signals fed to said entire plurality of pixels are all eliminated in said eliminating periods Te1, Te2, ···, Te(m-1); among said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n), a portion of the writing-in periods Ta1, Ta2, ···, Ta(m) and a portion of said eliminating periods Te1, Te2, ···, Te(m-1) overlap with each other; periods from the start of each of the writing-in periods Ta1, Ta2, ···, Ta(m-1) in said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) to the start of each of said eliminating periods Te1, Te2, ···, Te(m-1) are display periods Tr1, Tr2, ···, Tr(m-1); periods from the start of each of said eliminating periods Te1, Te2, ···, Te(m-1) to the start of each of the writing-in periods Ta1, Ta2, ···, Ta(m) in said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) are non-display periods Td1, Td2, ···, Td(m-1); periods from the start of each of the writing-in periods Ta1, Ta2, ···, Ta(m-1) in said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) to the start of the next writing-in periods of each of said writing-in periods Ta(m), Ta(m+1), ···, Ta(n), respectively. are display periods Tr(m), Tr(m+1), ···, Tr(n); in said display periods Tr1, Tr2, ···, Tr(n), said plurality of EL elements are selected by said digital data signals to luminesce or not luminesce; a length of said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) and a length of said (m-1) number of eliminating periods Te1, Te2, ···, Te(m-1) are the same: and ratios of the lengths of said display periods Tr1, Tr2, ···, Tr(n) are expressed as 2 0 :2 1 :···:.2 (n-1 ).

Claim 23

A device according to claim 22, wherein said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) are not overlapped with each other.

Claim 24

A device according to claim 22, wherein said (m-1) number of eliminating periods Te1, Te2, ···, Te(m-1) are not overlapped with each other.

Claim 25

A device according to claim 22, wherein said switching TFT, the EL driving TFT, and the eliminating TFT are at least one of an N channel TFT or a P channel TFT.

Claim 26

A device according to claim 22, wherein said EL driving TFT becomes an OFF state when an electric potential of said power supply line is applied to said gate electrode of said EL driving TFT.

Claim 27

A computer, which uses said electronic device according to claim 22.

Claim 28

A video camera, which uses said electronic device according to claim 22.

Claim 29

A DVD player, which uses said electronic device according to claim 22.

Claim 30

An electronic device comprising a source signal line driver circuit, a first gate signal line driver circuit, a second gate signal line driver circuit, a pixel portion including a plurality of pixels, a plurality of source signal lines connected to said source signal line driver circuit, a plurality of first gate signal lines connected to said first gate signal line driver circuit, a plurality of second gate signal lines connected to said second gate signal line driver circuit, and a power supply line held at a constant electric potential, wherein: said plurality of pixels each have a switching TFT, an EL driving TFT, an eliminating TFT and an EL element, said EL element includes a pixel electrode, an opposing electrode held at a constant electric potential, and an EL layer formed between said pixel electrode and said opposing electrode; a gate electrode of said switching TFT is connected to said first gate signal lines; one of a source region and a drain region of said switching TFT is connected to said plurality of source signal lines, another thereof is connected to a gate electrode of said EL driving TFT; a gate electrode of said eliminating TFT is connected to said second gate signal lines, one of a source region and a drain region of said eliminating TFT is connected to said power supply line, and another thereof is connected to a gate electrode of said EL driving TFT; one of a source region and a drain region of said EL driving TFT is connected to said power supply line, and another thereof is connected to a pixel electrode of said EL element; an (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) and an (m-1) number of eliminating periods Te1, Te2, ···, Te(m-1) (m is an arbitrary integer from 2 to (n)) are provided in 1 frame period; digital data signals from said source signal line driver circuit are fed to all said plurality of pixels through said plurality of source signal lines in said writing-in periods Ta1, Ta2, ···, Ta(n); the digital data signals fed to said plurality of pixels are all eliminated in said eliminating periods Te1, Te2, ···, Te(m-1), among said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n), a portion of the writing-in periods Ta1, Ta2, ···, Ta(m) and a portion of said eliminating periods Te1, Te2, ···, Te(m-1) overlap with each other; periods from the start of each of the writing-in periods Ta1, Ta2, ···, Ta(m-1) in said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) to the start of each of said eliminating periods Te1, Te2, ···, Te(m-1) are display periods Tr1, Tr2, ···, Tr(m-1); periods from the start of each of said eliminating periods Te1, Te2, ···, Te(m-1) to the start of each of the writing-in periods Tal, Ta2, ···, Ta(m) in said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) are non-display periods Td1, Td2, ···, Td(m-1); periods from the start of each of the writing-in periods Ta1, Ta2, ···, Ta(m-1) in said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) to the start of the next writing-in periods of each of said writing-in periods Ta(m), Ta(m+1), ···, Ta(n), respectively, are display periods Tr(m), Tr(m+1), ···; Tr(n); in said display periods Tr1, Tr2, , ···, Tr(n), said plurality of EL elements are selected by said digital data signals to luminesce or not luminesce; a length of said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) and a length of said (m-1) number of eliminating periods Te1, Te2, ···, Te(m-1) are the same; and ratios of the lengths of said display periods Tr1, Tr2, ···, Tr(n) are expressed as 2 0 :2 1 :···:.2 (n-1) .

Claim 31

A device according to claim 30, wherein said EL layer is a low molecular organic material or a polymer organic material.

Claim 32

A device according to claim 30, wherein said low molecular organic material is made of Alq 3 (tris-8-quinolilite-aluminum) or TPD (triphenylamine derivative).

Claim 33

A device according to claim 30, wherein said polymer organic material is made of PPV (polyphenylene vinylene), PVK (polyvinyl carbazole), or polycarbonate.

Claim 34

A device according to claim 30, wherein said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) are not overlapped with each other.

Claim 35

A device according to claim 30, wherein said (m-1) number of eliminating periods Te1, Te2, ···, Te(m-1) are not overlapped with each other.

Claim 36

A device according to claim 30, wherein said switching TFT, the EL driving TFT, and the eliminating TFT are at least one of an N channel TFT or a P channel TFT.

Claim 37

A device according to claim 30, wherein said EL driving TFT becomes an OFF state when an electric potential of said power supply line is applied to said gate electrode of said EL driving TFT.

Claim 38

A computer, which uses said electronic device according to any one of claims 1 through 19.

Claim 39

A video camera, which uses said electronic device according to claim 30.

Claim 40

A DVD player, which uses said electronic device according to claim 30.

Claim 41

An electronic device comprising a source signal line driver circuit, a first gate signal line driver circuit, a second gate signal line driver circuit, a pixel portion including a plurality of pixels, a plurality of source signal lines connected to said source signal line driver circuit, a plurality of first gate signal lines connected to said first gate signal line driver circuit, a plurality of second gate signal lines connected to said second gate signal line driver circuit. and a power supply line, wherein: said plurality of pixels each have a switching TFT, an EL driving TFT, an eliminating TFT, and an EL element; a gate electrode of said switching TFT is connected to said first gate signal lines; one of a source region and a drain region of said switching TFT is connected to said plurality of source signal lines, and another thereof is connected to a gate electrode of said EL driving TFT; a gate electrode of said eliminating TFT is connected to said second gate signal lines; one of a source region and a drain region of said eliminating TFT is connected to said power supply line, and another thereof is connected a gate electrode of said EL driving TFT; one of a source region and a drain region of said EL driving TFT is connected to said power supply line, and another thereof is connected to said EL element an (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) and an (m-1) number of eliminating periods Te1, Te2, ···, Te(m-1) (m is an arbitrary integer from 2 to (n)) are provided in 1 frame period,; digital data signals from said source signal line driver circuit are fed to all said plurality of pixels through said plurality of source signal lines in said writing-in periods Ta1, Ta2, ···, Ta(n); the digital data signals fed to said entire plurality of pixels are all eliminated in said eliminating periods Te1, Te2, ···, Te(m-1); among said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n), a portion of the writing-in periods Ta1, Ta-2, ···, Ta(m) and a portion of said eliminating periods Tel, Te2, ···, Te(m-1) overlap with each other; periods from the start of each of the writing-in periods Tal, Ta2, ···, Ta(m-1) in said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) to the start of each of said eliminating periods Te1, Te, ···, Te(m-1) are display periods Tr1, Tr2, ···, Tr(m-1); periods from the start of each of said eliminating periods Te1, Te2, ···, Te(m-1) to the start of each of the writing-in periods Ta1, Ta2, ···, Ta(m) in said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) are non-display periods Td1, Td2, ···, Td(m-1): periods from the start of each of the writing-in periods Ta1, Ta2, ···, Ta(m+1) in said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) to the start of the next writing-in periods of each of said writing-in periods Ta(m), Ta(m+1), ···, Ta(n), respectively, are display periods Tr(m), Tr(m+1), ···, Tr(n); in said display periods Tr1, Tr2, ···, Tr(n), said plurality of EL elements are selected by said digital data signals to luminesce or not luminesce; a length of said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) and a length of said (m-1) number of eliminating periods Te1, Te2, ···, Te(m-1) are the same; ratios of the lengths of said display periods Tr1, Tr2, ···, Tr(n) are expressed as 2 0 :2 1 :···:.2 (n-1) , and said display periods Tr1, Tr2, ···, Tr(n) appear in a random order.

Claim 42

A device according to claim 41, wherein said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) are not overlapped with each other.

Claim 43

A device according to claim 41, wherein said (m-1) number of eliminating periods Te1, Te2, ···, Te(m-1) are not overlapped with each other.

Claim 44

A device according to claim 41, wherein said switching TFT, the EL driving TFT, and the eliminating TFT are at least one of an N channel TFT or a P channel TFT.

Claim 45

A device according to claim 41, wherein said EL driving TFT becomes an OFF state when an electric potential of said power supply line is applied to said gate electrode of said EL driving TFT.

Claim 46

A computer, which uses said electronic device according to claim 41.

Claim 47

A video camera, which uses said electronic device according to claim 41.

Claim 48

A DVD player, which uses said electronic device according to claim 41.

Claim 49

An electronic device comprising a source signal line driver circuit, a first gate signal line driver circuit, a second gate signal line driver circuit, a pixel portion including a plurality of pixels, a plurality of source signal lines connected to said source signal line driver circuit, a plurality of first gate signal lines connected to said first gate signal line driver circuit, a plurality of second gate signal lines connected to said second gate signal line driver circuit, and a power supply line held at a constant electric potential, wherein: said plurality of pixels each have a switching TFT, an EL driving TFT, an eliminating TFT and an EL element;, said EL element includes a pixel electrode, an opposing electrode held at a constant electric potential, and an EL layer formed between said pixel electrode and opposing electrode; a gate electrode of said switching TFT is connected to said first gate signal lines; one of a source region and a drain region of said switching TFT is connected to said plurality of source signal lines, and another thereof is connected to a gate electrode of said EL driving TFT; a gate electrode of said eliminating TFT is connected to said second gate signal lines; one of a source region and a drain region of said eliminating TFT is connected to said power supply line, and another thereof is connected a gate electrode of said EL driving TFT; a source region and a drain region of said EL driving TFT, wherein one is connected to said power supply line whereas the other is connected to a pixel electrode of said EL element; an (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) and an (m-1) number of eliminating periods Te1, Te2, ···, Te(m-1) (m is an arbitrary integer from 2 to (n)) are provided in 1 frame period; digital data signals from said source signal line driver circuit are fed to all said plurality of pixels through said plurality of source signal lines in said writing-in periods Ta1, Ta2, ···, Ta(n); the digital data signals fed to said plurality of pixels are all eliminated in said eliminating periods Te1, Te2, ···, Te(m-1); among said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n), a portion of the writing-in periods Ta1, Ta2, ···, Ta(m) and a portion of said eliminating periods Te1, Te2, ···, Te(m-1) overlap with each other; periods from the start of each of the writing-in periods Ta1, Ta2, ···, Ta(m-1) in said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) to the start of each of said eliminating periods Te1, Te2, ···, Te(m-1) are display periods Tr1, Tr2, ···, Tr(m-1); periods from the start of each of said eliminating periods Te1, Te2, ···, Te(m-1) to the start of each of the writing-in periods Ta1, Ta2, ···, Ta(m) in said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) are non-display periods Td1, Td2, ···, Td(m-1); periods from the start of each of the writing-in periods Ta1, Ta2, ···, Ta(m-1) in said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) to the start of the next writing-in periods of each of said writing-in periods Ta(m), Ta(m+1), ···, Ta(n), respectively, are display periods Tr(m), Tr(m+1), ···, Tr(n); in said display periods Tr1, Tr2, ···, Tr(n), said plurality of EL elements are selected by said digital data signals to luminesce or not luminesce; a length of said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) and a length of said (m-1) number of eliminating periods Te1, Te2, ···, Te(m-1) are the same; ratios of the lengths of said display periods Tr1, Tr2, ···, Tr(n) are expressed as 2 0 :2 1 :···:.2 (n-1) ; and said display periods Tr1, Tr2, ···, Tr(n) appear in a random order.

Claim 50

A device according to claim 49, wherein said EL layer is a low molecular organic material or a polymer organic material.

Claim 51

A device according to claim 49, wherein said low molecular organic material is made of Alq 3 (tris-8-quinolilite-aluminum) or TPD (triphenylamine derivative).

Claim 52

A device according to claim 49, wherein said polymer organic material is made of PPV (polyphenylene vinylene), PVK (polyvinyl carbazole), or polycarbonate.

Claim 53

A device according to claim 49, wherein said (n) number of writing-in periods Ta1, Ta2, ···, Ta(n) are not overlapped with each other.

Claim 54

A device according to claim 49, wherein said (m-1) number of eliminating periods Te1, Te2, ···, Te(m-1) are not overlapped with each other.

Claim 55

A device according to claim 49, wherein said switching TFT, the EL driving TFT, and the eliminating TFT are at least one of an N channel TFT or a P channel TFT.

Claim 56

A device according to claim 49, wherein said EL driving TFT becomes an OFF state when an electric potential of said power supply line is applied to said gate electrode of said EL driving TFT.

Claim 57

A computer, which uses said electronic device according to claim 49.

Claim 58

A video camera, which uses said electronic device according to claim 49.

Claim 59

A DVD player, which uses said electronic device according to claim 49.

Claim 60

An electronic device comprising a source signal line driver circuit, a first gate signal line driver circuit, a second gate signal line driver circuit, and a pixel portion including a plurality of pixels, wherein said plurality of pixels have a plurality of EL elements, and wherein respective drives of said plurality of EL elements are controlled by a digital data signal outputted from said source signal line driver circuit, a first selecting signal outputted from said first gate signal line driver circuit, and a second selecting signal outputted from said second gate signal line driver circuit.

Claim 61

A computer, which uses said electronic device according to claim 60.

Claim 62

A video camera, which uses said electronic device according to claim 60.

Claim 63

A DVD player, which uses said electronic device according to claim 60.

Claim 64

An electronic device comprising a source signal line driver circuit. a first gate signal line driver circuit, a second gate signal line driver circuit. and a pixel portion including a plurality of pixels, wherein said plurality of pixels includes a plurality of EL elements; and wherein a luminescing time of said EL element is controlled by a digital data signal outputted from said source signal line driver circuit, a first selecting signal outputted from said first gate signal line driver circuit, and a second selecting signal outputted from said second gate signal line driver circuit, to thereby perform gray-scale display.

Claim 65

A computer, which uses said electronic device according to claim 64.

Claim 66

A video camera, which uses said electronic device according to claim 64.

Claim 67

A DVD player, which uses said electronic device according to claim 64.