US7224625B2
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Method and circuit arrangement for controlling write access to a semiconductor memory
Assignee: Polaris Innovations Ltd
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Filing: 2005-04-29
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Granted: 2007-05-29
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Expires: 2025-04-29
Abstract
Abstract The invention relates to a method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets are written to the semiconductor memory per data burst, in which write access is initiated by a write command and the data packets which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal, where the data packets are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal, and where the data strobe write clock control signal has a defined state at the start of the write operation. The invention also relates to a circuit arrangement for carrying out the method.
Inventors
- 👤 Stefan Dietrich
- 👤 Thomas Hein
- 👤 Peter Schroegmeier
- 👤 Christian Weis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:04
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/409; G11C11/4096; G11C7/10; G11C7/1015; G11C7/1018; G11C7/1027; G11C7/1051; G11C7/1066; G11C7/1078; G11C7/1087; G11C2207/00; G11C2207/22; G11C2207/229
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
131 words
Method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets (D 0 –D 3 ) are written to the semiconductor memory per data burst (DB), in which write access is initiated by a write command (WR) and the data packets (D 0 –D 3 ) which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal (WDQS), where the data packets (D 0 –D 3 ) are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal (WDQS), and where the data strobe write clock control signal (WDQS) has a defined state at the start of the write operation.
Claim 2
Dependent Claim
131 words
Method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets (D 0 –D 3 ) are written to the semiconductor memory per data burst (DB), in which write access is initiated by a write command (WR) and the data packets (D 0 –D 3 ) which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal (WDQS), where the data packets (D 0 –D 3 ) are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal (WDQS), and where the data strobe write clock control signal (WDQS) has a defined state at the start of the write operation.
Claim 3
Dependent Claim
66 words
Method according to claim 1 , characterized in that the data strobe write clock control signal (WDQS) has a firmly defined first logic level (“1”) in the inactive state, and in that the data strobe write clock control signal (WDQS) changes from a firmly defined second logic level (“1”) to the first logic level (“0”) at a prescribable time at the start of a write operation.
Claim 4
Dependent Claim
79 words
Method according to claim 1 , characterized in that after a respective write command (WR) the counter state of a counter is incremented or decremented, starting at a starting value, upon every cycle of the data strobe write clock control signal (WDQS), and in that at the end of a write operation associated with the respective write command (WR) the counter state is reset to the starting value or to another starting value when a final value is reached.
Claim 5
Dependent Claim
23 words
Method according to claim 1 , characterized in that the data strobe write clock control signal (WDQS) is used to synchronize the counters.
Claim 6
Dependent Claim
48 words
Method according to claim 1 , characterized in that at least two successive gapless write commands (WR) are provided which are at a minimal distance from one another, the minimal distance being determined by the length of a data burst (DB) associated with a respective write command (WR).
Claim 7
Dependent Claim
92 words
Method according to claim 5 , characterized in that in a first mode of operation the counter state is reset to a first starting value (“0”) if two successive write commands are at a distance from one another which is greater than the minimal distance, and in that in a second mode of operation the counter state is reset to a second starting value (“2”), which has a greater magnitude than the first starting value (“0”), if gapless write commands (WR) are provided which are at a minimal distance from one another.
Claim 8
Dependent Claim
57 words
Method according to claim 1 , characterized in that the write command (WR) and the duration of two successive write commands (WR) are used to derive a control signal (SG) which stipulates whether a write operation corresponding to a write command (WR) is performed in the first mode of operation or in the second mode of operation.
Claim 9
Dependent Claim
29 words
Method according to claim 7 , characterized in that the duration is determined by counting the falling and/or rising edges of the data strobe write clock control signal (WDQS).
Claim 10
Dependent Claim
53 words
Method according to claim 6 , characterized in that the second starting value (“2”) is set on the basis of the length of a data burst (DB) and/or on the basis of the cycle of the data strobe write clock control signal (WDQS) and/or on the basis of the first starting value (“0”).
Claim 11
Dependent Claim
65 words
Method according to claim 6 , characterized in that the length of the data burst (DB) is four, and in that within the data burst (DB) four data packets (D 0 –D 3 ) per write command (WR) are latched, the first starting value being 0 and the second starting value being 2, and the final value at which the counter is reset being 5.
Claim 12
Dependent Claim
41 words
Method according to claim 6 , characterized in that an adjustable delay is provided for the counter, which delay sets the starting value of the counter to the second starting value (“2”) in the case of the second mode of operation.
Claim 13
Dependent Claim
94 words
Circuit arrangement for carrying out a method according to claim 1 , which is designed to control write access to a semiconductor memory, particularly to a DDR graphics memory, in which a multiplicity of data packets (D 0 –D 3 ) are written to the semiconductor memory per data burst (DB), having a control/synchronization device ( 10 ) whose input is connected to an input for the data strobe write clock control signal (WDQS) and for the write signal (WR) and which controls and/or synchronizes the write operation in the case of write access.
Claim 14
Dependent Claim
70 words
Circuit arrangement according to claim 12 , characterized in that the control/synchronization device ( 10 ) has a write synchronization counter ( 14 ) whose output produces an enable signal (DF) on the basis of the data strobe write clock control signal (WDQS) and the write signal (WR), said enable signal producing a write control signal for controlling the write operation in the presence of a counter enable signal (CEN).
Claim 15
Dependent Claim
98 words
Circuit arrangement according to claim 12 , characterized in that the data packets (D 0 –D 3 ) are latched by providing a shift register ( 15 ) whose data input is connected to an input connection for inputting the data packets (D 0 –D 3 ) from a data burst (DB), whose data output is connected to the semiconductor memory ( 16 ) for shifting the latched data packets (D 0 –D 3 ) into the semiconductor memory ( 16 ), and whose control side is connected to a control connection for inputting the write control signal.
Claim 16
Dependent Claim
55 words
Circuit arrangement according to claim 12 , characterized in that a counting device ( 20 ) is provided which uses the duration of two successive write commands (WR) to derive a control signal (SG) which stipulates whether a write operation takes place in the first mode of operation or in the second mode of operation.
Claim 17
Dependent Claim
43 words
Circuit arrangement according to claim 15 , characterized in that the counting device ( 20 ) has a first adjustable counter ( 31 ) for setting a delay, the delay being able to be set using a delay control signal ( 32 ).
Claim 18
Dependent Claim
87 words
Circuit arrangement according to claim 12 , characterized in that a second counter ( 40 ) is provided which, to change its counter state, has a bridging device ( 33 , 48 – 51 ) which can be actuated by the control signal (SG), the counter ( 40 ) being able to be operated in the first mode of operation or in the second mode of operation depending on the actuation of the bridging device ( 33 , 48 – 51 ) by the control signal (SG).
Claim 19
Dependent Claim
31 words
Circuit arrangement according to claim 13 , characterized in that at least one of the counters ( 14 , 31 , 40 ) is in the form of a ring counter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-05-28 | 2010-11-27 | 2011-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-05-28 | 2014-11-27 | 2015-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-05-28 | 2018-11-27 | 2019-05-29 | $7700.00 | Window Closed / Lapsed |