Configurable DDR write-channel phase advance and delay capability

Claim 1

A memory controller for a double data rate (DDR) synchronous dynamic random access memory (SDRAM), the memory controller comprising: a configuration register driven by an internal memory controller clock signal; a first programmable delay connected to the configuration register for receiving a first set of one or more bits from the configuration register and a double-speed clock signal having a frequency twice as large as the frequency of the internal memory controller clock signal; an XOR gate connected to the first programmable delay for receiving a phase-delayed double-speed clock signal from the first programmable delay and a second set of one or more bits from the configuration register; a first flip-flop (FF) receiving a write command load signal and driven by the internal memory controller clock signal; a first multiplexer receiving the output signal of the first FF and the write command load signal and controlled by a first control signal; a second programmable delay connected to the configuration register for receiving the first set of one or more bits from the configuration register and the output signal of the first multiplexer; a second FF receiving data mask and a low write data (DM/WDATA_L) signal and driven by an inverted signal of the internal memory controller clock signal; a third FF receiving data mask and a high write data (DM/WDATA_H) signal and driven by the internal memory controller clock signal; a fourth FF connected to the second programmable delay for receiving the output signal of the second programmable delay and driven by the output signal of the first programmable delay; a fifth FF connected to the fourth FF for receiving the output signal of the fourth FF and driven by the output signal of the first programmable delay; a sixth FF connected to the fifth FF for receiving the output signal of the fifth FF and driven by the output signal of the first programmable delay; an OR gate connected to the fourth FF and the sixth FF for receiving the output signal of the fourth FF and the output signal of the sixth FF; a seventh FF connected to the OR gate for receiving the output signal of the OR gate and driven by the output signal of the first programmable delay; an eighth FF connected to the OR gate for receiving the output signal of the OR gate and driven by the output signal of the first programmable delay; a ninth FF connected to the seventh FF for receiving the output signal of the seventh FF and driven by the output signal of the first programmable delay; a second multiplexer connected to the seventh FF and the ninth FF for receiving the output signal of the seventh FF and the output signal of the ninth FF and controlled by a third set of one or more bits from the configuration register; a tenth FF connected to the second multiplexer for receiving the output signal of the second multiplexer, outputting a write data strobe (DDR_WDQS), and driven by the output signal of the XOR gate; a third multiplexer connected to the second and third FFs for receiving the output signal of the second FF and the output signal of the third FF and controlled by the output signal of the eighth FF; an eleventh FF connected to the third multiplexer for receiving the output signal of the third multiplexer and driven by the output signal of the first programmable delay; a fourth multiplexer connected to the third multiplexer and the eleventh FF for receiving the output signal of the third multiplexer and the output signal of the eleventh FF and controlled by the third set of one or more bits from the configuration register; and a twelfth FF connected to the fourth multiplexer for receiving the output signal of the fourth multiplexer, outputting a write data mask and write data (DDR_DM/WDBUS) signal, and driven by the output signal of the XOR gate.