US7117292B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus and method to switch a FIFO between strobe sources
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 2004-04-12
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Granted: 2006-10-03
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Expires: 2024-04-12
Abstract
Abstract A first-in, first-out (FIFO) unit switches between strobe sources. The FIFO uses a multiplexer to switch between two or more strobes so that different data strobes may be used with the FIFO to strobe in the data. In one implementation, the FIFO uses four data latches to strobe in data bits and output a pair of data bits onto the internal bus each half clock cycle.
Inventors
- 👤 James D. Kelly
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:55
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10; G06F12/00; G06F12/02; G06F12/08; G06F12/0802
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
170 words
An apparatus comprising: a first-in, first-out buffer (FIFO) to strobe in data from a data source based on at least a first strobe signal or a second strobe signal, the data to be buffered for transfer onto a data bus having different timing than the first or second strobe rate, the strobe signals based on a bit transfer rate per strobe of the data source which is to be used to transfer the data to the FIFO, wherein the FIFO includes latches to latch in the data and output pairs of bits based on the timing of the data bus; and a select circuit to select between the strobe signals, including the first strobe signal and the second strobe signal, depending on the bit transfer rate per strobe of the data source, the first strobe signal to be selected when the data source has a first bit transfer rate per strobe and the second strobe to be selected when the data source has a second bit transfer rate per strobe.
Claim 2
Independent Claim
170 words
An apparatus comprising: a first-in, first-out buffer (FIFO) to strobe in data from a data source based on at least a first strobe signal or a second strobe signal, the data to be buffered for transfer onto a data bus having different timing than the first or second strobe rate, the strobe signals based on a bit transfer rate per strobe of the data source which is to be used to transfer the data to the FIFO, wherein the FIFO includes latches to latch in the data and output pairs of bits based on the timing of the data bus; and a select circuit to select between the strobe signals, including the first strobe signal and the second strobe signal, depending on the bit transfer rate per strobe of the data source, the first strobe signal to be selected when the data source has a first bit transfer rate per strobe and the second strobe to be selected when the data source has a second bit transfer rate per strobe.
Claim 3
Dependent Claim
13 words
The apparatus of claim 1 , wherein the select circuit is a multiplexer.
Claim 4
Dependent Claim
23 words
The apparatus of claim 1 , wherein the select circuit is to receive a select signal from a value stored in a register.
Claim 5
Dependent Claim
23 words
The apparatus of claim 1 further including a register to store a programmable value used to select between the first and second strobes.
Claim 6
Dependent Claim
52 words
The apparatus of claim 1 , wherein the FIFO is comprised of four latches to strobe in four bits of data and output a pair of bits onto the data bus during a first portion of a clock cycle and another pair of bits during a second portion of the clock cycle.
Claim 7
Dependent Claim
42 words
The apparatus of claim 1 further including a second select circuit disposed in a data path of the incoming data to introduce delay in the data path to maintain phase relationship between the incoming data and the first or second strobe selected.
Claim 8
Dependent Claim
117 words
An integrated circuit comprising: an interim first-in, first-out buffer (FIFO) to strobe in data from a memory based on a first strobe signal or a second strobe signal, the strobe signals based on a bit transfer rate per strobe of the memory which is to be used to transfer the data to the FIFO; and a select circuit to select between the first strobe signal and the second strobe signal depending on the bit transfer rate per strobe of the memory, the first strobe signal to be selected when the memory has a first bit transfer rate per strobe and the second strobe to be selected when the memory has a second bit transfer rate per strobe.
Claim 9
Dependent Claim
117 words
An integrated circuit comprising: an interim first-in, first-out buffer (FIFO) to strobe in data from a memory based on a first strobe signal or a second strobe signal, the strobe signals based on a bit transfer rate per strobe of the memory which is to be used to transfer the data to the FIFO; and a select circuit to select between the first strobe signal and the second strobe signal depending on the bit transfer rate per strobe of the memory, the first strobe signal to be selected when the memory has a first bit transfer rate per strobe and the second strobe to be selected when the memory has a second bit transfer rate per strobe.
Claim 10
Dependent Claim
14 words
The integrated circuit of claim 7 , wherein the select circuit is a multiplexer.
Claim 11
Dependent Claim
23 words
The integrated circuit of claim 8 , wherein the multiplexer is to receive a select signal from a value stored in a register.
Claim 12
Dependent Claim
30 words
The integrated circuit of claim 8 further including a register to store a programmable value to be used by the multiplexer to select between the first and second strobe signals.
Claim 13
Dependent Claim
37 words
The integrated circuit of claim 8 , wherein the FIFO is comprised of latches to latch in the data and output pairs of bits onto an internal data bus based on timing of the internal data bus.
Claim 14
Dependent Claim
54 words
The integrated circuit of claim 8 , wherein the FIFO is comprised of four latches to strobe in four bits of data and output a pair of bits onto an internal data bus during a first portion of a clock cycle and another pair of bits during a second portion of the clock cycle.
Claim 15
Dependent Claim
42 words
The integrated circuit of claim 8 further including a second multiplexer disposed in a data path of the incoming data to introduce delay in the data path to maintain phase relationship between the incoming data and the first or second strobe selected.
Claim 16
Independent Claim
106 words
A method comprising: generating a plurality of strobes to accommodate data sources that have different bit transfer rates per strobe, in order to transfer data to a buffer at a bit transfer rate of a particular data source which is coupled to the buffer for data transfer; selecting one strobe from the plurality of strobes to allow data transfer from the particular data source to the buffer at a bit transfer rate of the particular data source; and receiving incoming data from the particular data source using the selected one strobe to receive the incoming data at the bit transfer rate of the particular data source.
Claim 17
Independent Claim
106 words
A method comprising: generating a plurality of strobes to accommodate data sources that have different bit transfer rates per strobe, in order to transfer data to a buffer at a bit transfer rate of a particular data source which is coupled to the buffer for data transfer; selecting one strobe from the plurality of strobes to allow data transfer from the particular data source to the buffer at a bit transfer rate of the particular data source; and receiving incoming data from the particular data source using the selected one strobe to receive the incoming data at the bit transfer rate of the particular data source.
Claim 18
Dependent Claim
22 words
The method of claim 14 further including multiplexing the plurality of strobes and using a select signal for selecting the one strobe.
Claim 19
Dependent Claim
24 words
The method of claim 15 further including delaying the incoming data to maintain phase relationship between the incoming data and the selected one strobe.
Claim 20
Dependent Claim
34 words
The method of claim 16 , wherein the receiving incoming data includes latching in the data and outputting pairs of bits based onto an internal data bus based on timing of the data bus.
Claim 21
Dependent Claim
52 words
The method of claim 16 , wherein the receiving incoming data includes latching to strobe in four bits of data and outputting a pair of bits onto an internal data bus during a first portion of a clock cycle and another pair of bits during a second portion of the clock cycle.
References Cited (Backward Citations)
US5956524A
Cited
US6385674B1
Cited
US5522064A
Cited
US5768560A
Cited
US20030088611A1
Cited
US5761478A
Cited
US5761464A
Cited
US6085285A
Cited
US6529988B1
Cited
US20030053367A1
Cited
US20050005183A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2009-10-02 | 2010-04-03 | 2010-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-10-02 | 2014-04-03 | 2014-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-10-02 | 2018-04-03 | 2018-10-03 | $7700.00 | Window Closed / Lapsed |